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Details, datasheet, quote on part number:SN54ABT18502
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Datasheet text preview:
SN54ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C AUGUST 1992 REVISED AUGUST 1994
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Member of the Texas Instruments SCOPE TM Family of Testability Products Member of the Texas Instruments Widebus TM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Two Boundary-Scan Cells per I/O for Greater Flexibility State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation
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SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ Parallel-Signature Analysis at Inputs With Masking Option Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Device Identification Even-Parity Opcodes Packaged in 68-Pin Ceramic Quad Flat Package Using 25-mil Center-to-Center Spacings
SN54ABT18502 . . . HV PACKAGE (TOP VIEW)
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1A2 1A1 1OEAB GND 1LEAB 1CLKAB TDO VCC NC TMS 1CLKBA 1LEBA 1OEBA GND 1B1 1B2 1B3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 87 6 543 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
2A7 2A8 2A9 GND 2OEAB 2LEAB 2CLKAB TDI NC
NC No internal connection
VCC
SCOPE, Widebus, UBT, and EPIC-IIB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TCK 2CLKBA 2LEBA GND 2OEBA 2B9 2B8
Copyright © 1994, Texas Instruments Incorporated
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SN54ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C AUGUST 1992 REVISED AUGUST 1994
description
The SN54ABT18502 scan test device with 18-bit universal bus transceiver is a member of the Texas Instruments SCOPE TM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM universal bus transceiver. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE TM universal bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary-scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18502 is characterized for operation over the full military temperature range of 55°C to 125°C.
FUNCTION TABLE (normal mode, each register) INPUTS OEAB L L L L L H LEAB L L L H H X CLKAB L X X X A X L H L H X OUTPUT B B0 L H L H
Z A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. Output level before the indicated steady-state input conditions were established.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C AUGUST 1992 REVISED AUGUST 1994
functional block diagram
Boundary-Scan Register 1LEAB 1CLKAB 1OEAB 1LEBA 1CLKBA 1OEBA 5
4 7 66 67 65
C1 1D C1 1D
1A1
8
C1 1D C1 1D
63
1B1
One of Nine Channels
2LEAB 2CLKAB 2OEAB 2LEBA 2CLKBA 2OEBA
32 33 31 39
38 41
C1 1D C1 1D
2A1
20
C1 1D C1 1D
51
2B1
One of Nine Channels Bypass Register Boundary-Control Register Identification Register VCC 34 VCC 68 37 3 Instruction Register TDO
TDI
TMS TCK
TAP Controller
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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