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Details, datasheet, quote on part number:SN54ABT18640
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Datasheet text preview:
SN54ABT18640, SN74ABT18640 SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS
SCBS267C FEBRUARY 1994 REVISED JULY 1996
D D D D
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Members of the Texas Instruments SCOPE TM Family of Testability Products Members of the Texas Instruments WidebusTM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ Parallel-Signature Analysis at Inputs Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Device Identification Even-Parity Opcodes State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages
SN54ABT18640 . . . WD PACKAGE SN74ABT18640 . . . DGG OR DL PACKAGE (TOP VIEW)
description
The 'ABT18640 scan test devices with 18-bit inverting bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 1B7 GND 1B8 1B9 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 VCC 2B8 2B9 GND 2DIR TDO TMS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 2A1 2A2 2A3 2A4 GND 2A5 2A6 2A7 VCC 2A8 2A9 GND 2OE TDI TCK
In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers. Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE can be used to disable the device so that the buses are effectively isolated. In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE, Widebus, and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
· DALLAS, TEXAS 75265
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SN54ABT18640, SN74ABT18640 SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS
SCBS267C FEBRUARY 1994 REVISED JULY 1996
description (continued)
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN74ABT18640 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ABT18640 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT18640 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (normal mode, each 9-bit section) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT18640, SN74ABT18640 SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS
SCBS267C FEBRUARY 1994 REVISED JULY 1996
functional block diagram
Boundary-Scan Register 1DIR 1
1OE
56
1A1
55
2
1B1
One of Nine Channels
2DIR
26
2OE
31
2A1
43
14
2B1
One of Nine Channels
Bypass Register
Boundary-Control Register
Identification Register VCC TDI 30 VCC TMS 28 TAP Controller Instruction Register 27 TDO
TCK
29
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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