|
Details, datasheet, quote on part number:SN54ABT18646HV
| |
Datasheet text preview:
SN54ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVERS AND REGISTERS
SGBS306 AUGUST 1992 REVISED AUGUST 1994
· · · · · ·
Members of the Texas Instruments SCOPE TM Family of Testability Products Members of the Texas Instruments Widebus TM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Includes D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data Two Boundary-Scan Cells per I/O for Greater Flexibility State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation
·
·
SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP and HIGHZ Parallel-Signature Analysis at Inputs With Masking Option Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Device Identification Even-Parity Opcodes Packaged in 68-Pin Ceramic Quad Flat Package
HV PACKAGE (TOP VIEW)
1A2 1A1 1OE GND 1SAB 1CLKAB TDO VCC NC TMS 1CLKBA 1SBA 1DIR GND 1B1 1B2 1B3
9 87 6 5432 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VC C 2A1 2A2 2A3 GND 2A4 2A5 2A6
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
2A7 2A8 2A9 GND 2OE 2SAB 2CLKAB TDI NC
NC No internal connection
VCC
SCOPE, Widebus, and EPIC-B are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TCK 2CLKBA 2SBA GND 2DIR 2B9 2B8
Copyright © 1994, Texas Instruments Incorporated
41
SN54ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVERS AND REGISTERS
SGBS306 AUGUST 1992 REVISED AUGUST 1994
description
The SN54ABT18646 scan test device with 18-bit bus transceivers and registers is a member of the Texas Instruments SCOPETM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, the SN54ABT18646 is an 18-bit bus transceiver and register that allows for multiplexed transmission of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers and registers. Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses. Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN54ABT18646. In the test mode, the normal operation of the SCOPETM bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18646 is characterized over the full military temperature range of 55°C to 125°C.
FUNCTION TABLE (normal mode, each 9-bit section) INPUTS OE X X H H L L L L DIR X X X X L L H H CLKAB X L X X X X CLKBA X L X X X X SAB X X X X X X L H SBA X X X X L H X X Input Unspecified Input Input disabled Output Output Input Input disabled DATA I/O A1 THRU A9 B1 THRU B9 Unspecified Input Input Input disabled Input Input disabled Output Output OPERATION OR FUNCTION OR FUNCTION Store A, B unspecified Store B, A unspecified Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
Stored A data to B bus The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.
42
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVERS AND REGISTERS
SGBS306 AUGUST 1992 REVISED AUGUST 1994
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X X CLKBA X X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X X STORAGE FROM A, B, OR A AND B
SAB X X X
SBA X X X
OE L L
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
BUS A DIR L H
BUS A
43
|
|
