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Details, datasheet, quote on part number:SN54ABT8952
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Datasheet text preview:
SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
SCBS121D AUGUST 1992 REVISED JULY 1996
D D D D D D D D D D D D D
Members of the Texas Instruments SCOPE TM Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Functionally Equivalent to 'BCT2952 and 'ABT2952 in the Normal-Function Mode SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ Parallel-Signature Analysis at Inputs With Masking Option Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Even-Parity Opcodes Two Boundary-Scan Cells Per I/O for Greater Flexibility State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Shrink Small-Outline (DL) and Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)
SN54ABT8952 . . . JT PACKAGE SN74ABT8952 . . . DL OR DW PACKAGE (TOP VIEW)
CLKAB CLKENAB OEAB A1 A2 A3 GND A4 A5 A6 A7 A8 TDO TMS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CLKBA CLKENBA OEBA B1 B2 B3 B4 VCC B5 B6 B7 B8 TDI TCK
SN54ABT8952 . . . FK PACKAGE (TOP VIEW)
B1 B2 B3 B4 V CC B5 B6 OEBA CLKENBA CLKBA CLKAB CLKENAB OEAB A1
5 6 7 8 9 10 4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
description
The 'ABT8952 scan test devices with octal registered bus transceivers are members of the Texas Instruments SCOPE TM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
B7 B8 TDI TCK TMS TDO A8
In the normal mode, these devices are functionally equivalent to the 'BCT2952 and 'ABT2952 octal registered bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal registered bus transceivers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A2 A3 GND A4 A5 A6 A7
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
SCBS121D AUGUST 1992 REVISED JULY 1996
description (continued)
Data flow in each direction is controlled by clock (CLKAB and CLKBA), clock-enable (CLKENAB and CLKENBA), and output-enable (OEAB and OEBA) inputs. For A-to-B data flow, A-bus data is stored in the associated registers on the low-to-high transition of CLKAB, provided that CLKENAB is low. Otherwise, if CLKENAB is high or CLKAB remains at a static low or high level, the register contents are not changed. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses CLKBA, CLKENBA, and OEBA. In the test mode, the normal operation of the SCOPE TM registered bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990. Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54ABT8952 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT8952 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (normal mode, each register) INPUTS OEAB L L L L H CLKENAB L L H X X CLKAB X L X A L H X X OUTPUT B L H B0 B0
X Z A-to-B data flow is shown; B-to-A data flow is similar but uses OEBA, CLKENBA, and CLKBA.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
SCBS121D AUGUST 1992 REVISED JULY 1996
functional block diagram
Boundary-Scan Register OEBA 26
CLKENBA
27
CLKBA
28
OEAB
3
CLKENAB
2
CLKAB
1
MUX G1 1 1 A1 4
C1 1D
25 C1 1D MUX G1 1 1
B1
One of Eight Channels
Bypass Register
Boundary-Control Register VCC TDI 16 Instruction Register 13 TDO
VCC TMS 14 TAP Controller
TCK
15
Pin numbers shown are for the DL, DW, and JT packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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