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Details, datasheet, quote on part number:SN54ABT8996JT
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SN54ABT8996, SN74ABT8996 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C AUGUST 1994 REVISED APRIL 1999
D D D D D D D D D D D D
Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture Extend Scan Access From Board Level to Higher Levels of System Integration Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test 10-Bit Address Space Provides for Up to 1021 User-Specified Board Addresses Bypass (BYP) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols Connect (CON) Pin Provides Indication of Primary-to-Secondary Connection High-Drive Outputs (32-mA IOH, 64-mA IOL) Support Backplane Interface at Primary and High Fanout at Secondary Package Options Include Plastic SmallOutline (DW) and Thin Shrink SmallOutline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT)
SN54ABT8996 . . . JT PACKAGE SN74ABT8996 . . . DW OR PW PACKAGE (TOP VIEW)
A4 A3 A2 A1 A0 BYP GND PTDO PTCK PTMS PTDI PTRST
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
A5 A6 A7 A8 A9 VCC CON STDI STCK STMS STDO STRST
SN54ABT8996 . . . FK PACKAGE (TOP VIEW)
A1 A0 BYP NC GND PTDO PTCK
A2 A3 A4 NC A5 A6 A7
432 5 6 7 8 9 10 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
A8 A9 VC C NC CON STDI STCK
PTMS PTDI
NC No internal connection
description
The 'ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TITM) SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Standard 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level. Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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STRST STDO STMS
PTRST NC
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SN54ABT8996, SN74ABT8996 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C AUGUST 1994 REVISED APRIL 1999
description (continued)
Most operations of the ASP are synchronous to the primary test clock (PTCK) input. This PTCK signal always is buffered directly onto the secondary test clock (STCK) output. Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the assertion of the primary test reset (PTRST) input or by use of shadow protocol. The PTRST signal is always buffered directly onto the secondary test reset (STRST) output, ensuring that the ASP and its associated secondary TAP can be reset simultaneously. When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO is at high impedance, while PTDO is at high impedance, except during acknowledgement of a shadow protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset to the Test-Logic-Reset state. In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that matches that at the parallel address inputs (A9A0), the ASP serially retransmits its address at PTDO as an acknowledgement and then assumes the connected (ON) status, as above. If the received address does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgement. The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the same fashion as a non-matching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states. Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP) input. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up reset. This bypassing feature is especially useful in the board-test environment, since it allows the board-level automated test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP input is high, the ASP is free to respond to shadow protocols. Otherwise, when BYP is low, shadow protocols are ignored. Whether the connected status is achieved by use of shadow protocol or by use of BYP, this status is indicated by a low level at the connect (CON) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON output is high. The SN54ABT8996 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT8996 is characterized for operation from 40°C to 85°C.
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SN54ABT8996, SN74ABT8996 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C AUGUST 1994 REVISED APRIL 1999
FUNCTION TABLE INPUTS BYP L L H H H H H H PTRST L H L H H H H H SHADOW-PROTOCOL RESULT -- -- -- RESET MATCH NO MATCH HARD ERROR¶ DISCONNECT OUTPUTS STRST L H L H H H H H STCK PTCK PTCK PTCK PTCK PTCK PTCK PTCK PTCK STMS H PTMS H H PTMS STMS0§ STMS0§ STMS0§ STDO PTDI PTDI Z Z PTDI Z Z Z PTDO STDI STDI Z Z STDI Z Z Z CON L L H H L H H H PRIMARY-TO-SECONDARY CONNECT STATUS BYP/TRST BYP TRST RESET ON OFF OFF OFF
H H TEST SYNCHRONIZATION H PTCK PTMS PTDI Z L MULTICAST Shadow protocols are received serially via PTCK and PTDI and acknowledged serially via PTCK and PTDO under certain conditions in which PTMS is static low or static high (see shadow protocol). The result shown here follows any required acknowledgement. In normal operation of IEEE Std 1149.1-compliant architectures, it is recommended that TMS be high prior to release of TRST. The BYP/TRST connect status ensures that this condition is met at STMS regardless of the applied PTMS. Also, it is recommended that STMS be kept high for a minimum duration of 5 PTCK cycles following assertion of PTRST, either by maintaining PTRST low or by setting PTMS high. This ensures that ICs both with and without TRST inputs are moved to their Test-Logic-Reset TAP states. It is expected that in normal application, this condition will only occur when BYP is fixed at the low state. In such case, upon release of PTRST, the ASP immediately resumes the BYP connect status. § STMS level before indicated steady-state conditions were established ¶ The shadow protocol is well defined. Some variations in the protocol are tolerated (see protocol errors). Those that are not tolerated are considered hard errors and cause disconnect as indicated.
functional block diagram
PTCK 9 VCC PTRST 12 VCC PTMS 10 VCC C1 PTDI 11 VCC STDI 17 VCC BYP 6 8 PTDO 14 STDO S 1D 15 STMS 13 STRST 16 STCK
Shadow-Protocol Receive
VCC A9A0 2024, 15
Connect Control
18
CON
Shadow-Protocol Transmit Pin numbers shown are for the DW, JT, and PW packages.
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SN54ABT8996, SN74ABT8996 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C AUGUST 1994 REVISED APRIL 1999
Terminal Functions
TERMINAL NAME A9A0 DESCRIPTION Address inputs. The ASP compares addresses received via shadow protocol against the value at A9A0 to determine address match. The bit order is from most significant to least significant. An internal pullup at each A9A0 terminal forces the terminal to a high level if it has no external connection. Bypass input. A low input at BYP forces the ASP into BYP or BYP/TRST status, depending on PTRST being high or low, respectively. While BYP is low, shadow protocols are ignored. Otherwise, while BYP is high, the ASP is free to respond to shadow protocols. An internal pullup forces BYP to a high level if it has no external connection. Connect indicator (output). The ASP indicates secondary-scan-port activity (resulting from BYP, BYP/TRST, MULTICAST, or ON status) by forcing CON to be low. Inactivity (resulting from OFF, RESET, or TRST status) is indicated when CON is high. Ground Primary test clock. PTCK receives the TCK signal required by IEEE Standard 1149.1-1990. The ASP always buffers PTCK to STCK. Shadow protocols are received/acknowledged synchronously to PTCK and connect-status changes invoked by shadow protocol are made synchronously to PTCK. Primary test data input. PTDI receives the TDI signal required by IEEE Standard 1149.1-1990. During appropriate TAP states, the ASP monitors PTDI for shadow protocols. During shadow protocols, data at PTDI is captured on the rising edge of PTCK. When a valid shadow protocol is received in this fashion, the ASP compares the received address against the A9A0 inputs. If the ASP detects a match, it outputs an acknowledgement and then connects its primary TAP terminals to its secondary TAP terminals. Under BYP, BYP/TRST, MULTICAST or ON status, the ASP buffers the PTDI signal to STDO. An internal pullup forces PTDI to a high level if it has no external connection. Primary test data output. PTDO transmits the TDO signal required by IEEE Standard 1149.1-1990. During shadow protocols, the ASP transmits any required acknowledgement via the PTDO. The acknowledgement data output at PTDO changes on the falling edge of PTCK. Under BYP, BYP/TRST, or ON status, the ASP buffers the PTDO signal from STDI. Under OFF, MULTICAST, RESET, or TRST status, PTDO is at high impedance. Primary test mode select. PTMS receives the TMS signal required by IEEE Standard 1149.1-1990. The ASP monitors the PTMS to determine the TAP-controller state. During stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test-Idle, Pause-DR, Pause-IR) the ASP can respond to shadow protocols. Under BYP, MULTICAST, or ON status, the ASP buffers the PTMS signal to STMS. An internal pullup forces PTMS to a high level if it has no external connection. Primary test reset. PTRST receives the TRST signal allowed by IEEE Standard 1149.1-1990. The ASP always buffers PTRST to STRST. A low input at PTRST forces the ASP to assume TRST or BYP/TRST status, depending on BYP being high or low, respectively. Such operation also asynchronously resets the internal ASP state to its power-up condition. Otherwise, while PTRST is high, the ASP is free to respond to shadow protocols. An internal pullup forces PTRST to a high level if it has no external connection. Secondary test clock. STCK retransmits the TCK signal required by IEEE Standard 1149.1-1990. The ASP always buffers STCK from PTCK. Secondary test data input. STDI receives the TDI signal required by IEEE Standard 1149.1-1990. Under BYP, BYP/TRST, or ON status, the ASP buffers STDI to PTDO. An internal pullup forces STDI to a high level if it has no external connection. Secondary test data output. STDO transmits the TDO signal required by IEEE Standard 1149.1-1990. Under BYP, BYP/TRST, MULTICAST, or ON status, the ASP buffers STDO from PTDI. Under OFF, RESET, or TRST status, STDO is at high impedance. Secondary test mode select. STMS retransmits the TMS signal required by IEEE Standard 1149.1-1990. Under BYP, MULTICAST, or ON status, the ASP buffers STMS from PTMS. When disconnected (as a result of OFF status), STMS maintains its last valid state until the ASP assumes BYP/TRST, RESET, or TRST status (upon which it is forced high) or the ASP again assumes BYP, MULTICAST, or ON status. Secondary test reset. STRST retransmits the TRST signal allowed by IEEE Standard 1149.1-1990. The ASP always buffers STRST from PTRST. Supply voltage
BYP
CON GND PTCK
PTDI
PTDO
PTMS
PTRST
STCK
STDI
STDO
STMS
STRST VCC
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SN54ABT8996, SN74ABT8996 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C AUGUST 1994 REVISED APRIL 1999
application information
In application, the ASP is used at each of several (serially-chained) groups of IEEE Std 1149.1-compliant devices. The ASP for each such group is assigned an address (via inputs A9A0) that is unique from that assigned to ASPs for the remaining groups. Each ASP is wired at its primary TAP to common (multidrop) TAP signals (sourced from a central IEEE Std 1149.1 bus master) and fans out its secondary TAP signals to the specific group of IEEE Std 1149.1-compliant devices with which it is associated. An example is shown in Figure 1.
IEEE Std 1149.1Compliant Device Chain
IEEE Std 1149.1Compliant Device Chain
IEEE Std 1149.1Compliant Device Chain
STDI STCK STMS STDO STRST
STDI STCK STMS STDO STRST
ADDR1
ADDR2
A9A0 ASP
A9A0 ASP
ADDR3
A9A0 ASP
PTDO PTCK PTMS PTDI PTRST
BYP
PTDO PTCK PTMS PTDI PTRST
IEEE Std 1149.1 Bus Master
TDI TCK TMS TDO TRST
PTDO PTCK PTMS PTDI PTRST
BYP
BYP
STDI STCK STMS STDO STRST
To Other Modules
Figure 1. ASP Application This application allows the ASP to be wired to a 4- or 5-wire multidrop test access bus, such as might be found on a backplane. Each ASP would then be located on a module, for example a printed-circuit board (PCB), which contains a serial chain of IEEE Std 1149.1-compliant devices and which would plug into the module-to-module bus (e.g., backplane). In the complete system, the ASP shadow protocols would allow the selection of the scan chain on a single module. The selected scan chain could then be controlled, via the multidrop TAP, as if it were the only scan chain in the system. Normal IR and DR scans can then be performed to accomplish the module test objectives. Once scan operations to a given module are complete, another module can be selected in the same fashion, at which time the ASP-based connection to the first module is dissolved. This procedure can be continued progressively for each module to be tested. Finally, one of two global addresses can be issued to either leave all modules unselected (disconnect address, DSA) or to deselect and reset scan chains for all modules (reset address, RSA). Additionally, in Pause-DR and Pause-IR TAP states, a third global address (test-synchronization address, TSA) can be invoked to allow simultaneous TAP-state changes and multicast scan-in operations to selected modules. This is especially useful in the former case, for allowing selected modules to be moved simultaneously to the Run-Test-Idle TAP state for module-level or module-to-module built-in self-test (BIST) functions, which operate synchronously to TCK in that TAP state, and in the latter case, for scanning common test setup/data into multiple like modules.
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