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Details, datasheet, quote on part number:SN54ABTH162260WD
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Datasheet text preview:
SN54ABTH162260, SN74ABTH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D JUNE 1992 REVISED MAY 1997
D D D D D D D D D D D
Members of the Texas Instruments WidebusTM Family B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABTH162260 . . . WD PACKAGE SN74ABTH162260 . . . DL PACKAGE (TOP VIEW)
description
OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 LE2B SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OE2B LEA2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 LEA1B OE1B
The 'ABTH162260 are 12-bit to 24-bit multiplexed D-type latches used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. These devices are also useful in memory-interleaving applications. Three 12-bit I/O ports (A1A12, 1B11B12, and 2B12B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ABTH162260, SN74ABTH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D JUNE 1992 REVISED MAY 1997
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABTH162260 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABTH162260 is characterized for operation from 40°C to 85°C. Function Tables
B TO A (OEB = H) INPUTS 1B H L X X X X X 2B X X X H L X X SEL H H H L L L X LE1B H H L X X X X LE2B X X X H H L X OEA L L L L L L H OUTPUT A H L A0 H L A0 Z
A TO B (OEA = H) INPUTS A H L H L H L X X X X X LEA1B H H H H L L L X X X X LEA2B H H L L H H L X X X X OE1B L L L L L L L H L H L OE2B L L L L L L L H H L L OUTPUTS 1B H L H L 1B0 1B0 1B0 Z Active Z Active 2B H L 2B0 2B0 H L 2B0 Z Z Active Active
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABTH162260, SN74ABTH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D JUNE 1992 REVISED MAY 1997
logic diagram (positive logic)
LE1B LE2B LEA1B LEA2B OE2B 2 27 30 55 56
OE1B
29
OEA SEL
1 28 C1
A1
8
G1 1 1
23 1D
1B1
C1 1D 6 2B1
C1 1D
C1 1D
To 11 Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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