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Details, datasheet, quote on part number:SN54ABTH162460WD
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Datasheet text preview:
SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS241E FEBRUARY 1993 REVISED MAY 1997
D D D D D D D D D D
Members of the Texas Instruments WidebusTM Family B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABTH162460 . . . WD PACKAGE SN74ABTH162460 . . . DL PACKAGE (TOP VIEW)
description
The 'ABTH162460 are 4-bit to 1-bit multiplexed registered transceivers used in applications where four separate data paths must be multiplexed onto or demultiplexed from a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications.
LEAB1 LEAB2 LEBA GND LEB1 LEB2 VCC CLKBA OEB CLKAB GND 1A 2A CE_SEL0 CE_SEL1 3A 4A GND CLKENAB CLKENB CLKENBA VCC LEB3 LEB4 GND OEA LEAB3 LEAB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OEB1 OEB2 SEL0 GND 1B1 1B2 VCC 1B3 1B4 2B1 GND 2B2 2B3 2B4 3B1 3B2 3B3 GND 3B4 4B1 4B2 VCC 4B3 4B4 GND SEL1 OEB3 OEB4
Five 4-bit I/O ports (1A4A, 1B14, 2B14, 3B14, and 4B14) are available for address and/or data transfer. The output-enable (OEB, OEB1OEB4, and OEA) inputs control the bus-transceiver functions. These control signals also allow 4-bit or 16-bit control, depending on the OEB level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS241E FEBRUARY 1993 REVISED MAY 1997
description (continued)
Address and/or data information can be stored using the internal storage latches/flip-flops. The latch-enable (LEB1LEB4, LEBA, and LEAB1LEAB4) and clock/clock-enable (CLK/CLKEN) inputs are used to control data storage. When either one of the latch-enable inputs is high, the latch is transparent (clock is a don't care as long as the latch enable is high). When the latch-enable input goes low (providing that the clock does not transit from low to high), the data present at the inputs is latched and remains latched until the latch-enable input is returned high. When the clock enable is low and the corresponding latch enable is low, data can be clocked on the low-to-high transition of the clock. When either the clock enable or the corresponding latch enable is high, the clock is a don't care. Four select (SEL0, SEL1, CE_SEL0, and CE_SEL1) pins are provided to multiplex data (A port), or to select one of four clock enables (B port). This allows the user the flexibility of controlling one bit at a time. The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABTH162460 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABTH162460 is characterized for operation from 40°C to 85°C. Function Tables
A-TO-B OUTPUT ENABLE INPUTS OEB H H L OEBn H L H OUTPUT Bn Z Z Z Active
L L n = 1, 2, 3, 4
A-TO-B STORAGE (assuming OEB = L, OEBn = L) INPUTS CLKENAB X X L L L L L H CE_SEL1 X X X L L H H X CE_SEL0 X X X L H L H X CLKAB H or L H or L L LEAB1 H H L L L L L L LEAB2 L H L L L L L L LEAB3 L H L L L L L L LEAB4 L L L L L L L L B1 A A A0 A A0 A0 A0 A0 OUTPUTS B2 A0 A A0 A0 A A0 A0 A0 B3 A0 A A0 A0 A0 A A0 A0 B4 A0 A0 A0 A0 A0 A0 A A0
This table does not cover all the latch-enable cases since they have similar results.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS241E FEBRUARY 1993 REVISED MAY 1997
Function Tables (Continued)
B-TO-A STORAGE (before point P) INPUTS CLKENB X X X X CLKBA X X X X LEB1 H L L L LEB2 L H L L LEB3 L L H L LEB4 L L L H SEL1 L L H H L L L L L L L H H L L L L L L L L H SEL0 L H L H L H L H L H L P B1 B2 B3 B4 B1 B2 B3 B4 B10 B20 B30 B40
H H Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (after point P) INPUTS CLKENBA X X X H L L L CLKBA X X X X L LEBA X H H L L L L OEA H L L L L L L B X L H X L H X OUTPUT A Z L H A0 L H
A0 Output level before the indicated steady-state input conditions were established
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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