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Details, datasheet, quote on part number:SN54ABTH182504AHV
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Datasheet text preview:
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C AUGUST 1993 REVISED JULY 1996
D D D D D D D
Members of the Texas Instruments SCOPE TM Family of Testability Products Members of the Texas Instruments WidebusTM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors B-Port Outputs of 'ABTH182504A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-B TM BiCMOS Design
D D
D
One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ Parallel-Signature Analysis at Inputs Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Device Identification Even-Parity Opcodes Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings
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87
A1 GND OEBA LEBA TDO VCC NC TMS CLKBA CLKENBA B1 GND B2 B3 B4
6 543 2 1 68 67 66 65 64 63 62 61
SN54ABTH18504A, SN54ABTH182504A . . . HV PACKAGE (TOP VIEW)
A3 A2
A4 A5 A6 GND A7 A8 A9 A10 NC VCC A11 A12 A13 GND A14 A15 A16
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
B5 B6 B7 GND B8 B9 B10 VCC NC B11 B12 B13 B14 GND B15 B16 B17
A17 A18 A19 GND A20 CLKENAB CLKAB TDI NC
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE, Widebus, UBT, and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TCK LEAB OEAB GND B20 B19 B18
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
VCC
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C AUGUST 1993 REVISED JULY 1996
SN74ABTH18504A, SN74ABTH182504A . . . PM PACKAGE (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
A4 A5 A6 GND A7 A8 A9 A10 VCC A11 A12 A13 GND A14 A15 A16
A3 A2 A1 GND OEBA LE B A TD O V CC TMS C LK B A C LK E N B A B1 GND B2 B3 B4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
B5 B6 B7 GND B8 B9 B10 VCC B11 B12 B13 B14 GND B15 B16 B17
description
The 'ABTH18504A and 'ABTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE TM universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPETM universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
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A17 A18 A19 GND A20 CLKENAB CLKAB TDI VCC TCK LEAB OEAB GND B20 B19 B18
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C AUGUST 1993 REVISED JULY 1996
description (continued)
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The B-port outputs of 'ABTH182504A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot. The SN54ABTH18504A and SN54ABTH182504A are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABTH18504A and SN74ABTH182504A are characterized for operation from 40°C to 85°C.
FUNCTION TABLE (normal mode, each register) INPUTS OEAB L L L L L L H LEAB L L L L H H X CLKENAB L L L H X X X CLKAB L X X X X A X L H X L H X OUTPUT B B0 L H B0 L H
Z A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKENBA, and CLKBA. Output level before the indicated steady-state input conditions were established
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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