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Details, datasheet, quote on part number:SN54ABTH182652A
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Datasheet text preview:
SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS167D AUGUST 1993 REVISED JULY 1996
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Members of the Texas Instruments SCOPE TM Family of Testability Products Members of the Texas Instruments Widebus TM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors B-Port Outputs of 'ABTH182652A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-B TM BiCMOS Design
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One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ Parallel-Signature Analysis at Inputs Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Device Identification Even-Parity Opcodes Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings
SN54ABTH18652A, SN54ABTH182652A . . . HV PACKAGE (TOP VIEW)
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1A2 1A1 1OEBA GND 1SAB 1CLKAB TDO VCC NC TMS 1CLKBA 1SBA 1OEAB GND 1B1 1B2 1B3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 87 6 5432 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
2A7 2A8 2A9 GND 2OEBA 2SAB 2CLKAB TDI NC
NC No internal connection
VCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE, Widebus, and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TCK 2CLKBA 2SBA GND 2OEAB 2B9 2B8
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS167D AUGUST 1993 REVISED JULY 1996
SN74ABTH18652A, SN74ABTH182652A . . . PM PACKAGE (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1A 2 1A 1 1OEBA GND 1S A B 1 C LK A B TD O V CC TMS 1 C LK B A 1S B A 1OEAB GND 1B 1 1B 2 1B 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
description
The 'ABTH18652A and 'ABTH182652A scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments SCOPE TM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE TM bus transceivers and registers. Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow, but uses CLKBA, SBA, and OEBA inputs. Since the OEBA input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions that are performed with the 'ABTH18652A and 'ABTH182652A.
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2A7 2A8 2A9 GND 2OEBA 2SAB 2CLKAB TDI VCC TCK 2CLKBA 2SBA GND 2OEAB 2B9 2B8
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS167D AUGUST 1993 REVISED JULY 1996
description (continued)
In the test mode, the normal operation of the SCOPE TM bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The B-port outputs of 'ABTH182652A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot. The SN54ABTH18652A and SN54ABTH182652A are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABTH18652A and SN74ABTH182652A are characterized for operation from 40°C to 85°C.
FUNCTION TABLE (normal mode, each 9-bit section) INPUTS OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CLKAB L L X X X X X CLKBA L L X X X X X SAB X X X X X X X X L H H SBA X X X X X X L H X X H A1 A9 Input disabled Input Input Input Unspecified Output Output Output Input Input Output DATA I/O B1 B9 Input disabled Input Unspecified Output Input Input Input Input Output Output Output OPERATION OR FUNCTION OR FUNCTION Isolation Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers Real-time B data to A bus Stored B data to A bus Real-time A data to B bus Stored A data to B bus Stored A data to B bus and stored B data to A bus
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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