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Details, datasheet, quote on part number:SN54ACT3632HFP
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Datasheet text preview:
SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS310A SEPTEMBER 1996 REVISED APRIL 1998
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Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA Flags Synchronized by CLKA
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Released as DESC SMD (Standard Microcircuit Drawing) 5962-9562801QYA IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Low-Power 0.8-µm Advanced CMOS Technology Supports Clock Frequencies up to 50 MHz Fast Access Times of 13 ns Packaged in 132-Pin Ceramic Quad Flat Package
description
The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths. The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A. The SN54ACT3632 is characterized for operation over the full military temperature range of 55°C to 125°C. For more information on this device family, see the following application reports:
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FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005) Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS310A SEPTEMBER 1996 REVISED APRIL 1998
HFP PACKAGE (TOP VIEW)
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VC C B15 B14 B13 B12 GND NC NC
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118 131 129 127 125 123 121 119 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC NC VCC C LK B ENB W/RB CSB GND IRB ORB A FB AEB VCC MBF1 MBB R S T2 FS 1 GND FS 0 R S T1 MBA MBF2 AEA AFA VCC ORA IRA CSA W/RA ENA C LK A GND NC
NC NC A35 A34 A33 A32 V CC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
NC No internal connection
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NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS310A SEPTEMBER 1996 REVISED APRIL 1998
functional block diagram
MBF1 Mail1 Register Port-A Control Logic
512 × 36 SRAM
RST1
FIFO1, Mail1 Reset Logic
Output Register
Input Register
CLKA CSA W/RA ENA MBA
36
Write Pointer
Read Pointer
IRA AFA FIFO1 36 FS0 FS1 A0A35 ORA AEA
Status-Flag Logic
ORB AEB
9 FIFO2
ProgrammableFlag Offset Registers
B0B35
Status-Flag Logic
IRB AFB
Read Pointer
Write Pointer
36
Output Register
Input Register
512 × 36 SRAM
FIFO2, Mail2 Reset Logic
RST2
Port-B Control Logic
Mail2 Register MBF2
CLKB CSB W/RB ENB MBB
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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