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Part: SN54ACT3641HFP
Category:
Logic
-> FIFOs
-> Synchronous FIFOs
Description: ti SN54ACT3641, 1024 X 36 Synchronous Fifo Memory
Company: Texas Instruments, Inc.
Datasheet: Download SN54ACT3641HFP datasheet File size : 214 kB
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Datasheet text preview:
SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A AUGUST 1995 REVISED APRIL 1998
D D D D D D D D
Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36 Synchronous Read-Retransmit Capability Mailbox Register in Each Direction Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic Input-Ready and Almost-Full Flags Synchronized by CLKA
D D D D D D
Output-Ready and Almost-Empty Flags Synchronized by CLKB Low-Power 0.8 µm Advanced CMOS Technology Supports Clock Frequencies up to 50 MHz Fast Access Times of 15 ns Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9560801QYA and 5962-9560801NXD Package Options include 132-Pin Ceramic Quad Flat (HFP) and 120-Pin Plastic Quad Flat (PCB) Packages
description
The SN54ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 15 ns. The 1024 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion is also possible in word depth. The SN54ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input. The SN54ACT3641 is characterized for operation over the full military temperature range of 55°C to 125°C. For more information on this device family, see the following application reports:
· · ·
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A AUGUST 1995 REVISED APRIL 1998
HFP PACKAGE (TOP VIEW)
17 16 15 14 13 12 11 10 9
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VC C B15 B14 B13 B12 GND NC NC
NC NC VCC C LK B ENB W/RB CSB GND MBF1 GND MBB NC VCC R FM RTM FS1/SEN FSO/SD GND RST MBA MBF2 VCC AE AF VCC OR IR CSA W/RA ENA C LK A GND NC
8 7 6 5 4 3 2 126 124 122 120 118 1 132 130 128 129 121 119 131 127 125 123 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC A35 A34 A33 A32 V CC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
NC No internal connection
2
NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
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SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A AUGUST 1995 REVISED APRIL 1998
PCB PACKAGE (TOP VIEW)
NC No internal connection
GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC
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B7 B8 B9 B10 B11
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
A35 A34 A33 A32 VC C A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VC C A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VC C A12
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
GND C LK A E NA W/RA C SA IR OR VCC AF AE VCC MBF2 MBA R ST GND FS0/SD FS1/SEN RTM R FM VCC NC MBB GND MBF1 GND C SB W/RB E NB C LK B VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VC C B15 B14 B13 B12 GND
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SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A AUGUST 1995 REVISED APRIL 1998
functional block diagram
MBF1 Mail1 Register Port-A Control Logic
1024 × 36 SRAM
RST
Reset Logic
Synch Retransmit L o gi c
Output Register
Input Register
CLKA CSA W/RA ENA MBA
36
RTM RFM
Write Pointer A0 A35 IR AF
Read Pointer
B0 B35 Status-Flag Logic OR AE
FS0/SD FS1/SEN 10
Flag-Offset Register Port-B Control Logic Mail2 Register
CLKB CSB W/RB ENB MBB
MBF2
4
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SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A AUGUST 1995 REVISED APRIL 1998
Terminal Functions
TERMINAL NAME A0 A35 AE AF B0 B35 CLKA CLKB CSA CSB ENA ENB I/O I/O O O I/O I I I I I I DESCRIPTION Port-A data. The 36-bit bidirectional data port for side A. Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less than or equal to the value in the almost-empty offset register (X). Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO is less than or equal to the value in the almost-full offset register (Y). Port-B data. The 36-bit bidirectional data port for side B. Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA. Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB. Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0 A35 outputs are in the high-impedance state when CSA is high. Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0 B35 outputs are in the high-impedance state when CSB is high. Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. Flag offset select 1/serial enable, flag offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset-register programming. During a device reset, FS1/SEN and FS0/SD select the flag offset-programming method. Three offset-register programming methods are available: automatically load one of two preset values, parallel load from port A, and serial load. I When serial load is selected for flag offset-register programming, FS1/SEN is used as an enable synchronous to the low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into the X-and Y-offset registers. The number of bit writes required to program the offset registers is 20. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset. Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0 B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO data for output. Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by a reset. Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by a reset. Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory. Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset the read pointer to the beginning retransmit location and output the first selected retransmit data. Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection. Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO out of retransmit mode.
FS1/SEN, FS0/SD
IR MBA MBB
O I I
MBF1
O
MBF2
O
OR
O
RFM RST
I I
RTM
I
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