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Details, datasheet, quote on part number:SN54ACT374
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| Part: | SN54ACT374 |
| Category: | Logic => Flip-Flops => CMOS/BiCMOS->AC/ACT Family |
| Description: | Octal D-type Edge-triggered Flip-flops With 3-state Outputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN54ACT374 datasheet File size : 307 kB |
| Request For quote: | Find where to buy SN54ACT374
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Datasheet text preview:
SN54ACT374, SN74ACT374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS539F OCTOBER 1995 REVISED NOVEMBER 2002
D D D D
4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 10 ns at 5 V Inputs Are TTL-Voltage Compatible
SN54ACT374 . . . J OR W PACKAGE SN74ACT374 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 'ACT374 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
SN54ACT374 . . . FK PACKAGE (TOP VIEW)
1D 1Q OE VCC 2D 2Q 3Q 3D 4D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PDIP N SOIC DW DW 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW CDIP J 55°C to 125°C CFP W LCCC FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74ACT374N SN74ACT374DW SN74ACT374DWR SN74ACT374NSR SN74ACT374DBR SN74ACT374PWR SNJ54ACT374J SNJ54ACT374W SNJ54ACT374FK TOP-SIDE MARKING SN74ACT374N ACT374 ACT374 AD374 AD374 SNJ54ACT374J SNJ54ACT374W
SNJ54ACT374FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
4Q GND CLK 5Q 5D
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SN54ACT374, SN74ACT374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS539F OCTOBER 1995 REVISED NOVEMBER 2002
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE CLK 1 11
C1 1D 3 1D
2
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT374, SN74ACT374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS539F OCTOBER 1995 REVISED NOVEMBER 2002
recommended operating conditions (see Note 3)
SN54ACT374 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 VCC VCC 24 24 8 0 0 MAX 5.5 SN74ACT374 MIN 4.5 2 0.8 VCC VCC 24 24 8 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 µA 50 µA VOH IOH = 24 mA 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 µA 50 µA VOL IOL = 24 mA 24 mA IOL = 50 mA IOL = 75 mA IOZ II ICC ICC VO = VCC or GND VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at GND or VCC VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 0.6 ±0.25 ±0.1 4 ±5 ±1 80 1.6 0.1 0.1 0.36 0.36 0.1 0.1 0.44 0.5 1.65 1.65 ±2.5 ±1 40 1.5 µA µA µA mA pF MIN 4.4 5.4 3.86 4.86 TA = 25°C TYP MAX 4.49 5.49 SN54ACT374 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX SN74ACT374 MIN 4.4 5.4 3.76 4.76 V MAX UNIT
Ci VI = VCC or GND 5V 4.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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