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Part: SN54ACT563
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: Octal D-type Transparent Latches With 3-state Outputs
Company: Texas Instruments, Inc.
Datasheet: Download SN54ACT563 datasheet File size : 214 kB
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Datasheet text preview:
SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS550A NOVEMBER 1995 REVISED 1996
D D D D D
Inputs Are TTL-Voltage Compatible 3-State Inverted Outputs Drive Bus Lines Directly Flow-Through Architecture to Optimize PCB Layout EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (N) and Ceramic (J) DIPs
SN54ACT563 . . . J OR W PACKAGE SN74ACT563 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE
description
The 'ACT563 are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs are set to the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components.
SN54ACT563 . . . FK PACKAGE (TOP VIEW)
2D 1D OE VCC 3D 4D 5D 6D 7D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q 2Q 3Q 4Q 5Q 6Q
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ACT563 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ACT563 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q L H Q0 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1996, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
8D GND CLK 8Q 7Q
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SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS550A NOVEMBER 1995 REVISED 1996
logic symbol
OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 3 4 5 6 7 8 9 EN C1 1D 1 19 18 17 16 15 14 13 12
logic diagram (positive logic)
OE LE 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q To Seven Other Channels 1D 2 C1 1D 19 1Q 1 11
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . 1.6 W N package . . . . . . . . . . . . . . . . . . . 1.3 W PW package . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS550A NOVEMBER 1995 REVISED 1996
recommended operating conditions (see Note 3)
SN54ACT563 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 55 0 0 4.5 2 0.8 VCC VCC 24 24 8 125 40 0 0 MAX 5.5 SN74ACT563 MIN 4.5 2 0.8 VCC VCC 24 24 8 85 MAX 5.5 UNIT V V V V V mA mA ns/V °C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 µA 50 µA VOH IOH = 24 mA 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 µA 50 µA VOL IOL = 24 mA 24 mA IOL = 50 mA IOL = 75 mA IOZ II ICC ICC VO = VCC or GND VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at GND or VCC VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 0.6 ±0.25 ±0.1 4 ±5 ±1 80 1.6 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±2.5 ±1 40 1.5 µA µA µA mA pF TA = 25°C MIN TYP MAX 4.4 5.4 3.86 4.86 4.49 5.49 SN54ACT563 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX SN74ACT563 MIN 4.4 5.4 3.76 4.76 V MAX UNIT
Ci VI = VCC or GND 5V 4.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 3 4 0 SN54ACT563 MIN 5 4.5 1.5 MAX SN74ACT563 MIN 3 4.5 0 MAX UNIT ns ns ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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