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Details, datasheet, quote on part number:SN54AHCT132J
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Datasheet text preview:
SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SCLS366F MAY 1997 REVISED JANUARY 2000
D D D D D D D D D
description
The 'AHCT132 devices positive-NAND gates. are quadruple
NC No internal connection
These devices perform the Boolean function Y = A · B or Y = A + B in positive logic. Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. The SN54AHCT132 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AHCT132 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y L H H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 2000, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
EPIC TM (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as 'AHCT00 Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN54AHCT132 . . . J OR W PACKAGE SN74AHCT132 . . . D, DB, DGV, N, OR PW PACKAGE (TOP VIEW)
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3B 3A 3Y
SN54AHCT132 . . . FK PACKAGE (TOP VIEW)
1B 1A NC VCC 4B 1Y NC 2A NC 2B
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4A NC 4Y NC 3B
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SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SCLS366F MAY 1997 REVISED JANUARY 2000
logic symbol
1A 1B 2A 2B 3A 3B 4A 4B 1 2 4 5 9 10 12 13 11 4Y 8 3Y 6 2Y & 3 1Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
logic diagram, each gate (positive logic)
A Y B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SCLS366F MAY 1997 REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54AHCT132 MIN VCC VI VO IOH IOL TA Supply voltage Input voltage Output voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 0 0 MAX 5.5 5.5 VCC 8 8 125 40 SN74AHCT132 MIN 4.5 0 0 MAX 5.5 5.5 VCC 8 8 85 UNIT V V V mA mA °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VT+ Positive-going input input threshold voltage VT Negative-going input input threshold voltage VT Hysteresis (VT+ VT) VOH VOL II ICC ICC IOH = 50 mA IOH = 8 mA IOL = 50 mA IOL = 8 mA VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND TEST CONDITIONS CONDITIONS VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 4.5 V 0 V to 5.5 V 5.5 V 5.5 V MIN 0.9 1 0.5 0.6 0.3 0.3 4.4 3.94 0.1 0.36 ±0.1 2 1.35 4.5 TA = 25°C TYP MAX 1.9 2.1 1.5 1.7 1.4 1.5 SN54AHCT132 MIN 0.9 1 0.5 0.6 0.3 0.3 4.4 3.8 0.1 0.5 ±1* 20 1.5 MAX 1.9 2.1 1.5 1.7 1.4 1.5 SN74AHCT132 MIN 0.9 1 0.5 0.6 0.3 0.3 4.4 3.8 0.1 0.44 ±1 20 1.5 10 MAX 1.9 V 2.1 1.5 V 1.7 1.4 V 1.5 V V UNIT
mA mA
mA pF
Ci VI = VCC or GND 5V 2 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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