|
Details, datasheet, quote on part number:SN54ALS175FK
| |
Datasheet text preview:
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MAY 1996
D D D D
'ALS174 and 'AS174 Contain Six Flip-Flops With Single-Rail Outputs 'ALS175 and 'AS175B Contain Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct-Clear Inputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators
SN54ALS174, SN54AS174 . . . J PACKAGE SN74ALS174, SN74AS174 . . . D OR N PACKAGE (TOP VIEW)
D D
Fully Buffered Outputs for Maximum Isolation From External Disturbances ('AS Only) Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54ALS175, SN54AS175B . . . J PACKAGE SN74ALS175, SN74AS175B . . . D OR N PACKAGE (TOP VIEW)
CLR 1Q 1D 2D 2Q 3D 3Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VC C 6Q 6D 5D 5Q 4D 4Q CLK
CLR 1Q 1Q 1D 2D 2Q 2Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VC C 4Q 4Q 4D 3D 3Q 3Q CLK
SN54ALS174, SN54AS174 . . . FK PACKAGE (TOP VIEW)
SN54ALS175A, SN54AS175B . . . FK PACKAGE (TOP VIEW)
1Q CLR NC VCC 6Q
1D 2D NC 2Q 3D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
6D 5D NC 5Q 4D
1Q 1D NC 2D 2Q
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q CLR NC VCC 4Q 4Q 4D NC 3D 3Q
3Q GND NC CLK 4Q
NC No internal connection
description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The 'ALS175 and 'AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
2Q GND NC CLK 3Q
Copyright © 1996, Texas Instruments Incorporated
1
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MAY 1996
description (continued)
These circuits are fully compatible for use with most TTL circuits. The SN54ALS174, SN54ALS175, SN54AS174, and SN54AS175B are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS174, SN74ALS175, SN74AS174, and SN74AS175B are characterized for operation from 0°C to 70°C.
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X L D X H L X OUTPUTS Q L H L Q0 Q H L H Q0
'ALS175 and 'AS175B only
logic symbols
'ALS174, 'AS174 CLR CLK 1D 2D 3D 4D 5D 6D 1 9 3 4 6 11 13 14 R C1 1D 2 5 7 10 12 15 1Q 2Q 3Q 4Q 5Q 6Q 4D 13 3D 12 2D 5 CLR CLK 1 9 'ALS175, 'AS175B R C1 2 1D 4 1D 3 7 6 10 11 15 14 3Q 4Q 4Q 1Q 1Q 2Q 2Q 3Q
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MAY 1996
logic diagrams (positive logic)
'ALS174, 'AS174 CLR 1 CLR 1 'ALS175, 'AS175B
CLK 1D
9 3
CLK 1D C1 R 2 1Q 1D
9 4
1D C1 R
2
1Q 1Q
3
To Five Other Channels Pin numbers shown are for the D, J, and N packages.
To Three Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS174, SN54ALS175 . . . . . . . . . . . . . . . . 55°C to 125°C SN74ALS174, SN74ALS175 . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS174 SN54ALS175 MIN VCC VIH VIL IOH IOL fclock tw Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency CLR low Pulse duration CLK high CLK low tsu th TA Setup time before CLK time before CLK Hold time, data after CLK Operating free-air temperature Data CLR inactive 0 15 12.5 12.5 15 8 0 55 125 4.5 2 0.8 0.4 4 40 0 10 10 10 10 6 0 0 70 ns ns °C ns NOM 5 MAX 5.5 SN74ALS174 SN74ALS175 MIN 4.5 2 0.8 0.4 8 50 NOM 5 MAX 5.5 V V V mA mA MHz UNIT
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
|
|
