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Details, datasheet, quote on part number:SN54ALS191AFK
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Datasheet text preview:
SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
D D D D D
Single Down / Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54ALS191A . . . J PACKAGE SN74ALS191A . . . D OR N PACKAGE (TOP VIEW)
B QB QA CTEN D/U QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VC C A CLK RCO MAX/MIN LOAD C D
description
The 'ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, the counter counts down.
SN54ALS191A . . . FK PACKAGE (TOP VIEW)
QA CTEN NC D/U QC
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
QB B NC VCC A CLK RCO NC MAX/MIN LOAD
NC No internal connection
Copyright © 1996, Texas Instruments Incorporated
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the conditions meeting the stable setup and hold times. These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on (current required by) clock drivers, for long parallel words.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QD GND NC D C
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SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
description (continued)
Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output (RCO) produces a low-level output pulse under those same conditions, but only while the clock input is low. The counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count (MAX/MIN) output can be used to accomplish look ahead for high-speed operation. The SN54ALS191A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS191A is characterized for operation from 0°C to 70°C.
logic symbol
CTEN D/U CLK LOAD A B C D 4 5 14 11 15 1 10 9 G1 CTRDIV16 12 MAX/MIN
M2 [DOWN] 2(CT=0)Z6 3(CT=15)Z6 M3 [UP] 1,2 / 1,3+ G4 6,1,4 C5 5D [1] [2] [4] [8]
13
RCO
3 2 6 7
QA QB QC QD
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
logic diagram (positive logic)
12 MAX/ MIN
CTEN D/U CLK LOAD A
4 13 5 RCO
14 11 15
S C1 1D R
3
QA
B
1
S C1 1D R
2
QB
C
10
S C1 1D R
6
QC
D
9 7
S C1 1D R
QD
Pin numbers shown are for the D, J, and N packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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