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Details, datasheet, quote on part number:SN54ALVTH16374
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| Part: | SN54ALVTH16374 |
| Category: | Logic => Flip-Flops => CMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage |
| Description: | 2.5-v/3.3v 16-bit Edge-triggered D-type Flip-flops With 3-state Outputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN54ALVTH16374 datasheet File size : 190 kB |
| Request For quote: | Find where to buy SN54ALVTH16374
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Datasheet text preview:
SN54ALVTH16374, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCES068F JUNE 1996 REVISED JANUARY 1999
D D D D D D D D D D
D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C High Drive (24/24 mA at 2.5-V and 32/64 mA at 3.3-V VCC) Power Off Disables Outputs, Permitting Live Insertion High-Impedance State During Power Up and Power Down Prevents Driver Conflict Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16374 . . . WD PACKAGE SN74ALVTH16374 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
1OE 1Q1 1Q2 GND 1Q3 1Q4 VC C 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VC C 2Q5 2Q6 GND 2Q7 2Q8 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1CLK 1D1 1D2 GND 1D3 1D4 VC C 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VC C 2D5 2D6 GND 2D7 2D8 2CLK
description
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1999, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ALVTH16374, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCES068F JUNE 1996 REVISED JANUARY 1999
description (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ALVTH16374 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALVTH16374 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 8-bit section) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALVTH16374, SN74ALVTH16374 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCES068F JUNE 1996 REVISED JANUARY 1999
logic diagram (positive logic)
1OE 1CLK 1 48 C1 1D 2 1Q1 2OE 2CLK 24 25 C1 2D1 36 1D 13
1D1
47
2Q1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output current in the low state, IO: SN54ALVTH16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74ALVTH16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH16374 MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 0 VCC 2.3 1.7 0.7 5.5 6 6 18 10 200 0 VCC TYP MAX 2.7 SN74ALVTH16374 MIN 2.3 1.7 0.7 5.5 8 8 24 10 TYP MAX 2.7 UNIT V V V V mA mA ns/V µs/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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