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Details, datasheet, quote on part number:SN54ALVTH16601WD
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Datasheet text preview:
SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES143A SEPTEMBER 1998 REVISED JULY 1999
D D D D D D D D D D D D D
UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus TM Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High-Drive (24/24 mA at 2.5-V and 32/64 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16601 . . . WD PACKAGE SN74ALVTH16601 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
OEAB LEAB A1 GND A2 A3 V CC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA
NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR and the DGVR package is abbreviated to VR.
description
The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UBT and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1999, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES143A SEPTEMBER 1998 REVISED JULY 1999
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16601 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALVTH16601 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS CLKENAB X X X H H L L L OEAB H L L L L L L L LEAB X H H L L L L L CLKAB X X X X X L or H A X L H X X L H X OUTPUT B Z L H B0 B0 L H
B0 A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Output level before the indicated steady-state input conditions were established
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES143A SEPTEMBER 1998 REVISED JULY 1999
logic diagram (positive logic)
OEAB 1
CLKENAB
56
CLKAB
55
LEAB
2
LEBA
28
CLKBA
30
CLKENBA
29
OEBA
27 CE 1D C1 CLK CE 1D C1 CLK 54 B1
A1
3
To 17 Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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