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Details, datasheet, quote on part number:SN54ALVTH16821WD
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Datasheet text preview:
SN54ALVTH16821, SN74ALVTH16821 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCES078E JULY 1996 REVISED JANUARY 1999
D D D D D D D D D D
D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C High-Drive (24/24 mA at 2.5-V and 32/64 mA at 3.3-V VCC) Power Off Disables Outputs, Permitting Live Insertion High-Impedance State During Power Up and Power Down Prevents Driver Conflict Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16821 . . . WD PACKAGE SN74ALVTH16821 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
1OE 1Q1 1Q2 GND 1Q3 1Q4 VC C 1Q5 1Q6 1Q7 GND 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VC C 2Q7 2Q8 GND 2Q9 2Q10 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1CLK 1D1 1D2 GND 1D3 1D4 VC C 1D5 1D6 1D7 GND 1D8 1D9 1D10 2D1 2D2 2D3 GND 2D4 2D5 2D6 VC C 2D7 2D8 GND 2D9 2D10 2CLK
description
The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1999, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ALVTH16821, SN74ALVTH16821 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCES078E JULY 1996 REVISED JANUARY 1999
description (continued)
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16821 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALVTH16821 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 10-bit section) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALVTH16821, SN74ALVTH16821 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCES078E JULY 1996 REVISED JANUARY 1999
logic diagram (positive logic)
1OE 1CLK 1 56
One of Ten Channels 1D1 55
C1 1D
2
1Q1
To Nine Other Channels
2OE 2CLK
28 29
One of Ten Channels 2D1 42
C1 1D
15
2Q1
To Nine Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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