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Details, datasheet, quote on part number:SN54AS821AJT
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Datasheet text preview:
SN54AS821A, SN74AS821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230A DECEMBER 1983 REVISED AUGUST 1995
· · · · · ·
Functionally Equivalent to AMD's AM29821 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs to Reduce dc Loading Effects Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54AS821A . . . JT PACKAGE SN74AS821A . . . DW OR NT PACKAGE (TOP VIEW)
description
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a highimpedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
3D 4D 5D NC 6D 7D 8D
OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VC C 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK
SN54AS821A . . . FK PACKAGE (TOP VIEW)
2D 1D OE NC VCC 1Q 2Q
4 5 6 7 8 9 10 3 2 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
3Q 4Q 5Q NC 6Q 7Q 8Q
NC No internal connection
OE does not affect the internal operation of the flip-flops. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS821A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AS821A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK L X D H L X X OUTPUT Q H L Q0 Z
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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· DALLAS, TEXAS 75265
9D 10D GND NC CLK 10Q 9Q
Copyright © 1995, Texas Instruments Incorporated
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SN54AS821A, SN74AS821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230A DECEMBER 1983 REVISED AUGUST 1995
logic symbol
OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 13 2 3 4 5 6 7 8 9 10 11 EN C1 1D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
logic diagram (positive logic)
OE 1
CLK
13
C1 1D 2 1D
23
1Q
To Nine Other Channels Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54AS821A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C SN74AS821A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AS821A, SN74AS821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230A DECEMBER 1983 REVISED AUGUST 1995
recommended operating conditions
SN54AS821A MIN VCC VIH VIL IOH IOL tw* tsu* th* Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK 9 7 0 4.5 2 0.8 24 32 8 6 0 NOM 5 MAX 5.5 SN74AS821A MIN 4.5 2 0.8 24 48 NOM 5 MAX 5.5 UNIT V V V mA mA ns ns ns °C
TA Operating free-air temperature 55 125 0 70 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4 5 V 4.5 VCC = 4 5 V 4.5 VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V II = 18 mA IOH = 2 mA IOH = 15 mA IOH = 24 mA IOL = 32 mA IOL = 48 mA VO = 2.7 V VI = 0.4 V VI = 7 V VI = 2.7 V VI = 0.4 V VO = 2.25 V Outputs high ICC Outputs low Outputs disabled 30 55 68 70 SN54AS821A MIN TYP MAX 1.2 VCC 2 2.4 2 0.25 0.5 0.35 50 50 0.1 20 0.5 112 88 109 113 30 55 68 70 0.5 50 50 0.1 20 0.5 112 88 109 113 mA 3.2 VCC 2 2.4 2 V µA µA mA µA mA mA 3.2 SN74AS821A MIN TYP MAX 1.2 UNIT V V
VOL IOZH IOZL II IIH IIL IO
All typical values are at VCC = 5 V, TA = 25°C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54AS821A, SN74AS821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230A DECEMBER 1983 REVISED AUGUST 1995
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 , R2 = 500 , TA = MIN to MAX SN54AS821A MIN tPLH tPHL tPZH tPZL tPHZ tPLZ CLK 3.5 Any Q Any Q Any Q 3.5 4 OE OE 4 1 1 MAX 9 14 12 13 10 10 SN74AS821A MIN 3.5 3.5 3 4 1 1 MAX 7.5 13 11 12 8 8 ns ns ns
PARAMETER
FROM (INPUT)
TO (OUTPUT)
UNIT
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AS821A, SN74AS821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230A DECEMBER 1983 REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V VCC S1 RL From Output Under Test CL (see Note A) RL Test Point R1 From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R2 Test Point RL = R1 = R2
LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR 3-STATE OUTPUTS
Timing Input tsu Data Input 1.3 V
3.5 V 1.3 V 0.3 V th 3.5 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
High-Level Pulse
3.5 V 1.3 V tw 1.3 V 0.3 V
Low-Level Pulse
3.5 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS
Output Control (low-level enabling) tPZL Waveform 1 S1 Closed (see Note B)
3.5 V 1.3 V 1.3 V 0.3 V tPLZ 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V 3.5 V Input tPLH In-Phase Output 1.3 V 1.3 V 1.3 V 0.3 V tPHL VOH 1.3 V VOL tPLH VOH 1.3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V VOL
[3.5 V
tPHZ tPZH Waveform 2 S1 Open (see Note B)
tPHL Out-of-Phase Output (see Note C)
[0 V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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