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Details, datasheet, quote on part number:SN54AS823AFK
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Datasheet text preview:
SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS231A JUNE 1984 REVISED AUGUST 1995
· · · · · ·
Functionally Equivalent to AMD's AM29823 and AM29824 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs to Reduce dc Loading Effects Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54AS823A . . . JT PACKAGE SN74AS823A . . . DW OR NT PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VC C 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK
description
These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers. With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking CLKEN high disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has inverting (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or the highimpedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS823A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AS823A and SN74AS824A are characterized for operation from 0°C to 70°C.
SN54AS823A . . . FK PACKAGE (TOP VIEW)
3D 4D 5D NC 6D 7D 8D
2D 1D OE NC VCC 1Q 2Q
4 5 6 7 8 9 10 3 2 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
3Q 4Q 5Q NC 6Q 7Q 8Q
SN74AS824A . . . DW OR NT PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND
NC No internal connection
Copyright © 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
9D CLR GND NC CLK CLKEN 9Q
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK
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SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS231A JUNE 1984 REVISED AUGUST 1995
Function Tables
SN54AS823A, SN74AS823A (each flip-flop) INPUTS OE L L L L H CLR L H H H X CLKEN X L L H X CLK X X X D X H L X X OUTPUT Q L H L Q0 Z
SN74AS824A (each flip-flop) INPUTS OE L L L L H CLR L H H H X CLKEN X L L H X CLK X X X D X H L X X OUTPUT Q L L H Q0 Z
logic symbols
SN54AS823A, SN74AS823A OE CLR CLKEN CLK 1 11 14 13 EN R G1 1C2 23 22 21 20 19 18 17 16 15 OE CLR CLKEN CLK 1 11 14 13 SN74AS824A EN R G1 1C2 23 22 21 20 19 18 17 16 15
1D 2D 3D 4D 5D 6D 7D 8D 9D
2 3 4 5 6 7 8 9 10
2D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q
1D 2D 3D 4D 5D 6D 7D 8D 9D
2 3 4 5 6 7 8 9 10
2D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS231A JUNE 1984 REVISED AUGUST 1995
logic diagrams (positive logic)
SN54AS823A, SN74AS823A OE CLR CLKEN 1 11 14
CLK 1D
13
R C1 23 1Q
2
1D
To Eight Other Channels SN74AS824A OE CLR CLKEN 1 11 14
CLK 1D
13
R C1 23 1Q
2
1D
To Eight Other Channels Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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