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Details, datasheet, quote on part number:SN54AS867FK
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Datasheet text preview:
SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C DECEMBER 1982 REVISED JANUARY 1995
· · · · ·
Fully Programmable With Synchronous Counting and Loading SN74ALS867A and AS867 Have Asynchronous Clear; SN74ALS869 and AS869 Have Synchronous Clear Fully Independent Clock Circuit Simplifies Use Ripple-Carry Output for n-Bit Cascading Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54AS867, SN54AS869 . . . JT PACKAGE SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 . . . DW OR NT PACKAGE (TOP VIEW)
description
These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positivegoing) edge of the clock waveform. These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
S0 S1 A B C D E F G H ENT GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VC C ENP QA QB QC QD QE QF QG QH CLK RCO
SN54AS867, SN54AS869 . . . FK PACKAGE (TOP VIEW)
B C D NC E F G
4 5 6 7 8 9 10
3
2 1 28 27 26 25 24 23 22 21 20
ENP QA QB QC QD NC QE QF QG
19 11 12 13 14 15 16 17 18
NC No internal connection
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined by the levels of the select (S0, S1) inputs as shown in the function table. ENT is fed forward to enable RCO. RCO thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages. Transitions at ENP and ENT are allowed regardless of the level of CLK. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the SN74ALS867A and AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q outputs until clocking occurs. For the AS867 and AS869, any time ENP and/or ENT is taken high, RCO either goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT is taken high, RCO either goes or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
H ENT GND NC RCO CLK QH
Copyright © 1995, Texas Instruments Incorporated
A S1 S0 NC VCC
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SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C DECEMBER 1982 REVISED JANUARY 1995
description (continued)
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE S1 L L H H S0 L H L H FUNCTION Clear Count down Load Count up
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C DECEMBER 1982 REVISED JANUARY 1995
logic symbols
SN74ALS867A S0 S1 ENT ENP CLK 1 2 11 23 14 0 1 G4 G5 CTRDIV 256 0 M 3 1,4CT=0 3,4CT=255
13
RCO
C6/1,4,5 /3,4,5 + 0R 2,6D 22 21 20 19 18 17 16 15 QA QB QC QD QE QF QG QH
A B C D E F G H
3 4 5 6 7 8 9 10
SN74ALS869 S0 S1 ENT ENP CLK 1 2 11 23 14 0 1 G4 G5 CTRDIV 256 0 M 3 1,4CT=0 3,4CT=255
13
RCO
C6/1,4,5 /3,4,5 + 0,6R 2,6D 22 21 20 19 18 17 16 15 QA QB QC QD QE QF QG QH
A B C D E F G H
3 4 5 6 7 8 9 10
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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