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Details, datasheet, quote on part number:SN54HC165W
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Datasheet text preview:
SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C DECEMBER 1982 REVISED MAY 1997
D D D D D
Complementary Outputs Direct Overriding Load (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54HC165 . . . J OR W PACKAGE SN74HC165 . . . D, N, OR PW PACKAGE (TOP VIEW)
description
The 'HC165 are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (AH) inputs that are enabled by a low level at the shift/load (SH/LD) input. The 'HC165 also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
SH/LD CLK E F G H QH GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC CLK INH D C B A SER QH
SN54HC165 . . . FK PACKAGE (TOP VIEW)
E F NC G H
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLK SH/LD NC VCC CLK INH D C NC B A
NC No internal connection FUNCTION CLK INH X X H Parallel load No change No change Shift
Copyright © 1997, Texas Instruments Incorporated
The SN54HC165 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74HC165 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS SH/LD L H H H H CLK X H X L
L Shift Shift = content of each internal register shifts toward serial output QH. Data at SER is shifted into the first register.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QH GND NC QH SER
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SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C DECEMBER 1982 REVISED MAY 1997
logic symbol
1 SH/LD CLK INH CLK SER A B C D E F G H 15 2 10 11 12 13 14 3 4 5 6 1D 9 7 QH QH SRG8 C1 [LOAD] 1 C2/
2D 1D 1D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages.
logic diagram (positive logic)
A SH/LD CLK INH CLK SER 1 15 2 10
S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R
B 11 12
C 13
D 14
E 3
F 4
G 5
H 6
9
QH
7
QH
Pin numbers shown are for the D, J, N, PW, and W packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C DECEMBER 1982 REVISED MAY 1997
typical shift, load, and inhibit sequence
CLK
CLK INH SER L
SH/LD A H L H L H
B C Data Inputs
D E
F G H QH QH
L H H H L Inhibit Load H L L H H L L H H L L H H L
Serial Shift
absolute maximum ratings over operating free-air temperature range
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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