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Details, datasheet, quote on part number:SN54HC166
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Datasheet text preview:
SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117C DECEMBER 1982 REVISED DECEMBER 2002
D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns ±4-mA Output Drive at 5 V
SN54HC166 . . . J OR W PACKAGE SN74HC166 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
D D D D
Low Input Current of 1 µA Max Synchronous Load Direct Overriding Clear Parallel-to-Serial Conversion
SN54HC166 . . . FK PACKAGE (TOP VIEW)
SER A B C D CLK INH CLK GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC SH/LD H QH G F E CLR
A SER NC VCC SH/LD B C NC D CLK INH
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
H QH NC G F
NC No internal connection
description/ordering information
These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift / load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero. ORDERING INFORMATION
TA PDIP N SOIC D to 85°C 40°C to 85°C SOP NS SSOP DB TSSOP PW CDIP J 55°C to 125°C CFP W LCCC FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74HC166N SN74HC166D SN74HC166DR SN74HC166NSR SN74HC166DBR SN74HC166PWR SNJ54HC166J SNJ54HC166W SNJ54HC166FK TOP-SIDE MARKING SN74HC166N HC166 HC166 HC166 HC166 SNJ54HC166J SNJ54HC166W
SNJ54HC166FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CLK GND NC CLR E
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SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117C DECEMBER 1982 REVISED DECEMBER 2002
FUNCTION TABLE INPUTS CLR L H H H H H SH/LD X X L H H X CLK INH X L L L L H CLK X L SER X X X H L X PARALLEL A...H X X a...h X X X OUTPUTS INTERNAL QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 QH L Q H0 h QGn QGn Q H0
logic diagram (positive logic)
A SH/LD SER 15 1 2 B 3 C 4 D 5 E 10 F 11 G 12 H 14
6 CLK INH 7 CLK 9 CLR
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
13 QH
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117C DECEMBER 1982 REVISED DECEMBER 2002
typical clear, shift, load, inhibit, and shift sequence
CLK CLK INH CLR SER SH/LD A B C Parallel Inputs D E F G H QH Serial Shift Clear H L H L H L H H H Inhibit Load H L H L H L H
Serial Shift
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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