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Details, datasheet, quote on part number:SN54HC166W
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Datasheet text preview:
SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B DECEMBER 1982 REVISED MAY 1997
D D D D
Synchronous Load Direct Overriding Clear Parallel-to-Serial Conversion Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54HC166 . . . J OR W PACKAGE SN74HC166 . . . D OR N PACKAGE (TOP VIEW)
description
The 'HC166 parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift / load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
SER A B C D CLK INH CLK GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC SH/LD H QH G F E CLR
SN54HC166 . . . FK PACKAGE (TOP VIEW)
A SER NC VCC SH/LD B C NC D CLK INH
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
H QH NC G F
NC No internal connection
The SN54HC166 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74HC166 is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CLK GND NC CLR E
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SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B DECEMBER 1982 REVISED MAY 1997
FUNCTION TABLE INPUTS CLR L H H H H H SH/LD X X L H H X CLK INH X L L L L H CLK X L SER X X X H L X PARALLEL A...H X X a...h X X X OUTPUTS INTERNAL QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 QH L Q H0 h QGn QGn Q H0
logic symbol
CLR SH/LD CLK INH CLK SER A B C D E F G H 6 7 1 2 3 4 5 10 11 12 14 13 QH 9 15 R SRG8
M1 [Shift] M2 [Load] 1 C3/1
1, 3D 2, 3D 2, 3D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B DECEMBER 1982 REVISED MAY 1997
logic diagram (positive logic)
A SH/LD SER 15 1 2 B 3 C 4 D 5 E 10 F 11 G 12 H 14
CLK INH CLK CLR
6 7 9
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
13 QH
Pin numbers shown are for the D, J, N, and W packages.
typical clear, shift, load, inhibit, and shift sequence
CLK CLK INH CLR SER SH/LD A B C Parallel Inputs D E F G H QH Serial Shift Clear H L H L H L H H H Inhibit Load H L H L H L H
Serial Shift
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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