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Details, datasheet, quote on part number:SN54HC174J
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Datasheet text preview:
SCLS119D - DECEMBER 1982 - REVISED SEPTEMBER 2003
SN54HC174, SN74HC174 HEX D TYPE FLIP FLOPS WITH CLEAR
D D D D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Contain Six Flip-Flops With Single-Rail Outputs Applications Include: - Buffer/Storage Registers - Shift Registers - Pattern Generators
SN54HC174 . . . J OR W PACKAGE SN74HC174 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
CLR 1Q 1D 2D 2Q 3D 3Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 6Q 6D 5D 5Q 4D 4Q CLK
description/ordering information
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
SN54HC174 . . . FK PACKAGE (TOP VIEW)
1D 2D NC 2Q 3D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q CLR NC VCC 6Q 6D 5D NC 5Q 4D
NC - No internal connection ORDERABLE PART NUMBER SN74HC174N SN74HC174D SN74HC174DR SN74HC174DT SN74HC174NSR SN74HC174DBR SN74HC174PW SN74HC174PWR SN74HC174PWT SNJ54HC174J SNJ54HC174W SNJ54HC174FK SNJ54HC174J SNJ54HC174W HC174 HC174 HC174 HC174
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
ORDERING INFORMATION
TA PACKAGE PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40°C to 85 C 85°C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 TOP-SIDE MARKING SN74HC174N
SNJ54HC174FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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3Q GND NC CLK 4Q
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SCLS119D - DECEMBER 1982 - REVISED SEPTEMBER 2003
SN54HC174, SN74HC174 HEX D TYPE FLIP FLOPS WITH CLEAR
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X L D X H L X OUTPUT Q L H L Q0
logic diagram (positive logic)
CLR 1
CLK 1D
9 3
1D C1 R 2 1Q
To Five Other Channels Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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· DALLAS, TEXAS 75265
SCLS119D - DECEMBER 1982 - REVISED SEPTEMBER 2003
SN54HC174, SN74HC174 HEX D TYPE FLIP FLOPS WITH CLEAR
recommended operating conditions (see Note 3)
SN54HC174 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC174 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 µA VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 TA = 25°C MIN TYP MAX 1.9 4.4 5.9 3.98 5.48 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 0.1 0.1 0.1 0.26 0.26 ±100 8 10 SN54HC174 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 160 10 MAX SN74HC174 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 80 10 nA µA pF V V MAX UNIT
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SCLS119D - DECEMBER 1982 - REVISED SEPTEMBER 2003
SN54HC174, SN74HC174 HEX D TYPE FLIP FLOPS WITH CLEAR
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V CLR low tw Pulse duration CLK high or low 4.5 V 6V 2V 4.5 V 6V 2V Data tsu Setup time before CLK CLR inactive 4.5 V 6V 2V 4.5 V 6V 2V th Hold time, data after CLK CLK 4.5 V 6V 80 16 14 80 16 14 100 20 17 100 20 17 0 0 0 TA = 25°C MIN MAX 6 31 36 120 24 20 120 24 20 150 30 25 150 30 25 0 0 0 SN54HC174 MIN MAX 4.2 21 25 100 20 17 100 20 17 125 25 21 125 25 21 0 0 0 ns ns ns SN74HC174 MIN MAX 5 25 29 MHz UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V CLR tpd CLK Any Any 4.5 V 6V 2V 4.5 V 6V 2V tt Any 4.5 V 6V MIN 6 31 36 TA = 25°C TYP MAX 9 44 50 58 17 14 58 17 14 38 8 6 160 32 27 160 32 27 75 15 13 SN54HC174 MIN 4.2 21 25 240 48 41 240 48 41 110 22 19 MAX SN74HC174 MIN 5 25 29 200 40 34 200 40 34 90 19 16 ns ns MHz MAX UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS No load TYP 27 UNIT pF
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· DALLAS, TEXAS 75265
SCLS119D - DECEMBER 1982 - REVISED SEPTEMBER 2003
SN54HC174, SN74HC174 HEX D TYPE FLIP FLOPS WITH CLEAR
PARAMETER MEASUREMENT INFORMATION
High-Level Pulse VCC 50% tw Low-Level Pulse VCC 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC 50% tPLH Reference Input tsu Data Input 50% 10% 90% 50% th 90% VCC 50% 10% 0 V tf Out-of-Phase Output VCC 0V In-Phase Output 50% 10% tPHL 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL 50% 0V
From Output Under Test
Test Point CL = 50 pF (see Note A)
Input
tr
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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