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Details, datasheet, quote on part number:SN54HC191FK
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Datasheet text preview:
SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
D D D D D
Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54HC191 . . . J OR W PACKAGE SN74HC191 . . . D OR N PACKAGE (TOP VIEW)
B QB QA CTEN D/U QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A CLK RCO MAX/MIN LOAD C D
description
The 'HC191 are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count-enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down.
SN54HC191 . . . FK PACKAGE (TOP VIEW)
QB B NC VCC A QA CTEN NC D/U QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLK RCO NC MAX/MIN LOAD
NC No internal connection
These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be easily cascaded by feeding RCO to CTEN of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation. The SN54HC191 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74HC191 is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QD GND NC D C
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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
logic symbol
CTEN D/U 14 11 15 1 10 9 4 5 G1 M3 [UP] CLK LOAD A B C D 1,2/1,3+ G4 C5 5D [1] [2] [4] [8] 3 2 6 7 QA QB QC QD 6,1,4 CTRDIV16 2(CT=0) Z6 3(CT=15) Z6 13 RCO 12 MAX/MIN
M2 [DOWN]
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B DECEMBER 1982 REVISED MAY 1997
logic diagram (positive logic)
12 4 13 D/U CLK LOAD A 5 14 11 15 S C1 1D R 1 2 3 RCO
MAX/MIN
CTEN
QA
B
S C1 1D R
QB
C
10 6
S C1 1D R
QC
D
9 7
S C1 1D R
QD
Pin numbers shown are for the D, J, N, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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