|
Details, datasheet, quote on part number:SN54HC193
| |
Datasheet text preview:
SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122C DECEMBER 1982 REVISED DECEMBER 2002
D D D D D D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 20 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear
SN54HC193 . . . J OR W PACKAGE SN74HC193 . . . D, N, NS, OR PW PACKAGE (TOP VIEW)
B QB QA DOWN UP QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A CLR BO CO LOAD C D
SN54HC193 . . . FK PACKAGE (TOP VIEW)
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high.
NC No internal connection
ORDERING INFORMATION
TA PDIP N 40°C to 85°C SOIC D SOP NS TSSOP PW CDIP J 55°C to 125°C CFP W PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tube Tube ORDERABLE PART NUMBER SN74HC193N SN74HC193D SN74HC193DR SN74HC193NSR SN74HC193PWR SNJ54HC193J SNJ54HC193W TOP-SIDE MARKING SN74HC193N HC193 HC193 HC193 SNJ54HC193J SNJ54HC193W
LCCC FK Tube SNJ54HC193FK SNJ54HC193FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QD GND NC D C
The 'HC193 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
QB B NC VCC A QA DOWN NC UP QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description/ordering information
CLR BO NC CO LOAD
1
SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122C DECEMBER 1982 REVISED DECEMBER 2002
description/ordering information (continued)
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD inputs. These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO) output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122C DECEMBER 1982 REVISED DECEMBER 2002
logic diagram (positive logic)
12 13 CLR UP DOWN LOAD A 14 5 4 11 15 S C1 1D R S R 3 QA CO BO
B
1 2
S C1 1D R
QB
C
10 6
S C1 1D R
QC
D
9 7
S C1 1D R
QD
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
|
|
