|
Details, datasheet, quote on part number:SN54HC193J
| |
| Part: | SN54HC193J |
| Category: | Logic => Counters => Binary Counters |
| Description: | ti SN54HC193, Synchronous 4-Bit Up/down Binary Counters With Dual Clock And Clear |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN54HC193J datasheet File size : 377 kB |
| Request For quote: | Find where to buy SN54HC193J
|
| |
Datasheet text preview:
SN54HC193, SN74HC193 4 BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122D - DECEMBER 1982 - REVISED OCTOBER 2003
D D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 20 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max
SN54HC193 . . . J OR W PACKAGE SN74HC193 . . . D, N, NS, OR PW PACKAGE (TOP VIEW)
D Look-Ahead Circuitry Enhances Cascaded D D D
Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear
SN54HC193 . . . FK PACKAGE (TOP VIEW)
NC - No internal connection
description/ordering information
The 'HC193 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. ORDERING INFORMATION
TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40°C to 85°C SOP - NS Reel of 2500 Reel of 250 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC193N SN74HC193D SN74HC193DR SN74HC193DT SN74HC193NSR SN74HC193PW SN74HC193PWR SN74HC193PWT SNJ54HC193J SNJ54HC193W SNJ54HC193FK SNJ54HC193J SNJ54HC193W HC193 HC193 HC193 TOP-SIDE MARKING SN74HC193N
SNJ54HC193FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QD GND NC D C
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
B QB QA DOWN UP QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A CLR BO CO LOAD C D
QB B NC VCC A QA DOWN NC UP QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLR BO NC CO LOAD
Copyright 2003, Texas Instruments Incorporated
1
SCLS122D - DECEMBER 1982 - REVISED OCTOBER 2003
SN54HC193, SN74HC193 4 BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
description/ordering information (continued)
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD inputs. These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO) output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC193, SN74HC193 4 BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122D - DECEMBER 1982 - REVISED OCTOBER 2003
logic diagram (positive logic)
12 13 CLR UP DOWN LOAD A 14 5 4 11 15 S C1 1D R S R 3 QA CO BO
B
1 2
S C1 1D R
QB
C
10 6
S C1 1D R
QC
D
9 7
S C1 1D R
QD
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SCLS122D - DECEMBER 1982 - REVISED OCTOBER 2003
SN54HC193, SN74HC193 4 BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
typical clear, load, and count sequence
The following sequence is illustrated below: 1. Clear outputs to 0 2. Load (preset) to binary 13 3. Count up to 14, 15, carry, 0, 1, and 2 4. Count down to 1, 0, borrow, 15, 14, and 13
CLR LOAD A B C D UP DOWN QA QB QC QD CO BO 0 13 14 15 0 Count Up 1 2 1 0 15 14 Count Down 13
Data Inputs
Data Outputs
Clear
Preset
NOTES: A. CLR overrides LOAD, data, and count inputs. B. When counting up, count-down input must be high; when counting down, count-up input must be high.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC193, SN74HC193 4 BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122D - DECEMBER 1982 - REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC193 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC193 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
|
|
