|
Details, datasheet, quote on part number:SN54HC193W
| |
Datasheet text preview:
SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122B DECEMBER 1982 REVISED MAY 1997
D D D D D
Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54HC193 . . . J OR W PACKAGE SN74HC193 . . . D OR N PACKAGE (TOP VIEW)
B QB QA DOWN UP QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A CLR BO CO LOAD C D
description
The 'HC193 are 4-bit synchronous, reversible, up/down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high.
SN54HC193 . . . FK PACKAGE (TOP VIEW)
QB B NC VCC A QA DOWN NC UP QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLR BO NC CO LOAD
NC No internal connection
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD inputs. These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO) output produces a low-level pulse while the count is maximum (9 or 15) and UP is low. The counters can then be easily cascaded by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter. The SN54HC193 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74HC193 is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
QD GND NC D C
1
SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122B DECEMBER 1982 REVISED MAY 1997
logic symbol
CLR UP 14 5 CT=0 2+ G1 1 G2 C3 3D [1] [2] [4] [8] 3 2 6 7 QA QB QC QD CTRDIV16 12 13
1CT=15 2CT=0
CO BO
DOWN LOAD A B C D
4 11 15 1 10 9
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SCLS122B DECEMBER 1982 REVISED MAY 1997
logic diagram (positive logic)
12 13 CLR UP DOWN LOAD A 14 5 4 11 15 S C1 1D R S R 3 QA CO BO
B
1 2
S C1 1D R
QB
C
10 6
S C1 1D R
QC
D
9 7
S C1 1D R
QD
Pin numbers shown are for the D, J, N, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
|
|
