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Details, datasheet, quote on part number:SN54HCT02J
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Datasheet text preview:
SN54HCT02, SN74HCT02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS065B NOVEMBER 1988 REVISED MAY 1997
D D
Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54HCT02 . . . J OR W PACKAGE SN74HCT02 . . . D OR N PACKAGE (TOP VIEW)
description
These devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A · B or Y = A + B in positive logic. The SN54HCT02 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74HCT02 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each gate) INPUTS A H X L B X H L OUTPUT Y L L H
1Y 1A 1B 2Y 2A 2B GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4Y 4B 4A 3Y 3B 3A
SN54HCT02 . . . FK PACKAGE (TOP VIEW)
1A 1Y NC VCC 4Y 1B NC 2Y NC 2A
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4B NC 4A NC 3Y
logic symbol
1A 1B 2A 2B 3A 3B 4A 4B 2 3 5 6 8 9 11 12 1
NC No internal connection
1
1Y
4
2Y
10
3Y
13
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages.
logic diagram (positive logic)
A Y B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
2B GND NC 3A 3B
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SN54HCT02, SN74HCT02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS065B NOVEMBER 1988 REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
recommended operating conditions
SN54HCT02 MIN VCC VIH VIL VI VO tt TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time Operating free-air temperature VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0 0 0 0 55 0.8 VCC VCC 500 125 NOM 5 MAX 5.5 SN74HCT02 MIN 4.5 2 0 0 0 0 40 0.8 VCC VCC 500 85 NOM 5 MAX 5.5 UNIT V V V V V ns °C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II ICC ICC Ci TEST CONDITIONS CONDITIONS VI = VIH or VIL or VI = VIH or VIL or VI = VCC or 0 VI = VCC or 0, IOH = 20 µA IOH = 4 mA IOL = 20 µA IOL = 4 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 0.1 0.26 ±100 2 2.4 10 SN54HCT02 MIN 4.4 3.7 0.1 0.4 ±1000 40 3 10 MAX SN74HCT02 MIN 4.4 3.84 0.1 0.33 ±1000 20 2.9 10 MAX UNIT V V nA µA mA pF
IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HCT02, SN74HCT02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS065B NOVEMBER 1988 REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd tt FROM (INPUT) A or B or TO (OUTPUT) Y Y VCC 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 11 10 9 8 20 18 15 14 SN54HCT02 MIN MAX 30 27 22 20 SN74HCT02 MIN MAX 25 22 19 17 UNIT ns ns
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS No load TYP 20 UNIT pF
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output 3V Input 1.3 V tPLH 1.3 V 10% tPHL Out-of-Phase Output 90% 1.3 V 10% tf 90% tr Input 1.3 V 0.3 V 2.7 V 2.7 V 3V 1.3 V 0.3 V 0 V tf tPLH 1.3 V 10% 90% tr VOH VOL 1.3 V 0V tPHL 90% VOH 1.3 V 10% V OL tf
LOAD CIRCUIT
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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