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Details, datasheet, quote on part number:SN54LV125AFK
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Datasheet text preview:
SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCES124D DECEMBER 1997 REVISED JULY 1998
D D D D D D
EPICTM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) 2 V at VCC, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VC C 4OE 4A 4Y 3OE 3A 3Y
SN54LV125A . . . FK PACKAGE (TOP VIEW)
1A 1OE NC VCC 4OE 1Y NC 2OE NC 2A
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description
The `LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation. These devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
4A NC 4Y NC 3OE
NC No internal connection
The SN54LV125A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LV125A is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1998, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
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SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCES124D DECEMBER 1997 REVISED JULY 1998
logic symbol
1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 10 9 13 12 8 3Y EN 1 3 6 1Y 2Y
11
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
1OE 1A 1 2 4 2OE 2A 5 6 2Y 4A 4OE 12 11 4Y 3 3OE 1Y 3A 10 9 13 8
3Y
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
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POST OFFICE BOX 655303
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SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCES124D DECEMBER 1997 REVISED JULY 1998
recommended operating conditions (see Note 4)
SN54LV125A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 High or low state 3-state VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 0 0 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC 5.5 50 2 8 16 50 2 8 16 200 100 0 0 0 0 0 MAX 5.5 SN74LV125A MIN 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC 5.5 50 2 8 16 50 2 8 16 200 100 ns/V mA µA mA V V MAX 5.5 UNIT V
VIH
High-level input voltage input voltage
VIL
Low-level input voltage input voltage
VI VO
Input voltage Output voltage voltage
V V µA
IOH
High-level output current output current
IOL
Low-level output current output current
t/v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature 55 125 40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 µA IOH = 2 mA IOH = 8 mA IOH = 16 mA IOL = 50 µA IOL = 2 mA IOL = 8 mA IOL = 16 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV125A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 0V 3.3 V 2 MIN VCC0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 ±5 20 5 2 TYP MAX SN74LV125A MIN VCC0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 ±5 20 5 µA µA µA µA pF V TYP MAX UNIT
VOH
V
VOL
II IOZ ICC Ioff Ci
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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