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Details, datasheet, quote on part number:SN54LVC373A
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Datasheet text preview:
SN54LVC373A, SN74LVC373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCAS295P JANUARY 1993 REVISED SEPTEMBER 2002
D D D D D D
Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.8 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
D D D
Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
VCC
1D 1Q OE VCC 2D 2Q 3Q 3D 4D
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE
1
OE
20 19 18 17 16 15 14 13 12
1Q 1D 2D 2Q 3Q 3D 4D 4Q
2 3 4 5 6 7 8 9 10 11
8Q 8D 7D 7Q 6Q 6D 5D 5Q
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
SN54LVC373A . . . J OR W PACKAGE SN74LVC373A . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW)
SN74LVC373A . . . RGY PACKAGE (TOP VIEW)
SN54LVC373A . . . FK PACKAGE (TOP VIEW)
description/ordering information
ORDERING INFORMATION
TA PDIP N QFN RGY SOIC DW DW 40°C to 85°C SOP NS SSOP DB TSSOP PW TVSOP DGV VFBGA GQN CDIP J 55°C to 125°C CFP W PACKAGE Tube Tape and reel Tube Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube ORDERABLE PART NUMBER SN74LVC373AN SN74LVC373ARGYR SN74LVC373ADW SN74LVC373ADWR SN74LVC373ANSR SN74LVC373ADBR SN74LVC373APWR SN74LVC373ADGVR SN74LVC373AGQNR SNJ54LVC373AJ SNJ54LVC373AW TOP-SIDE MARKING SN74LVC373AN LC373A LVC373A LVC373A LC373A LC373A LC373A LC373A SNJ54LVC373AJ SNJ54LVC373AW
LCCC FK Tube SNJ54LVC373AFK SNJ54LVC373AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
GND
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
LE
4Q GND LE 5Q 5D
1
SN54LVC373A, SN74LVC373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCAS295P JANUARY 1993 REVISED SEPTEMBER 2002
description/ordering information (continued)
The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
GQN PACKAGE (TOP VIEW) 1 A B C D E 2 3 4 A B C D E
terminal assignments
1 1Q 2D 3Q 4D GND 2 OE 7D 2Q 5D 4Q 3 VCC 1D 6Q 3D LE 4 8Q 8D 7Q 6D 5Q
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVC373A, SN74LVC373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCAS295P JANUARY 1993 REVISED SEPTEMBER 2002
logic diagram (positive logic)
OE 1
LE
11 C1 2
1D
3
1D
1Q
To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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