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Details, datasheet, quote on part number:SN54LVC540A
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Datasheet text preview:
SN54LVC540A, SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS297K JANUARY 1993 REVISED AUGUST 2002
D D D D D D D D D
A2 A1 OE1 VCC
description/ordering information
The SN54LVC540A octal buffer/driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC540A octal buffer/driver is designed for 1.65-V to 3.6-V VCC operation. These devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.
A3 A4 A5 A6 A7
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
OE2 Y1 Y2 Y3 Y4 Y5
Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.3 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model (C101)
SN54LVC540A . . . J OR W PACKAGE SN74LVC540A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW)
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
SN54LVC540A . . . FK PACKAGE (TOP VIEW)
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all outputs are in the high-impedance state. ORDERING INFORMATION
TA SOIC DW DW 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW TVSOP DGV CDIP J 55°C to 125°C CFP W PACKAGE Tube Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube ORDERABLE PART NUMBER SN74LVC540ADW SN74LVC540ADWR SN74LVC540ANSR SN74LVC540ADBR SN74LVC540APWR SN74LVC540ADGVR SNJ54LVC540AJ SNJ54LVC540AW TOP-SIDE MARKING LVC540A LVC540A LC540A LC540A LC540A SNJ54LVC540AJ SNJ54LVC540AW
LCCC FK Tube SNJ54LVC540AFK SNJ54LVC540AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A8 GND Y8 Y7 Y6
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SN54LVC540A, SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS297K JANUARY 1993 REVISED AUGUST 2002
description/ordering information (continued)
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE INPUTS OE1 L L H X OE2 L L X H A L H X X OUTPUT Y H L Z Z
logic diagram (positive logic)
OE1 OE2 1 19
A1
2
18
Y1
To Seven Other Channels
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVC540A, SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS297K JANUARY 1993 REVISED AUGUST 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVC540A MIN VCC Supply voltage voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage voltage High or low state 3-state VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 12 24 12 24 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 0 2 2 1.5 MAX 3.6 SN74LVC540A MIN 1.65 1.5 0.65 × VCC 1.7 2 0.35 × VCC 0.7 0.8 5.5 VCC 5.5 0 0 0 0.8 5.5 VCC 5.5 4 8 12 24 4 8 12 24 mA mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
IOH
High-level output current output current
IOL
Low-level output current output current
TA Operating free-air temperature 55 125 40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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