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Details, datasheet, quote on part number:SN54LVC646A
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Datasheet text preview:
SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS302I JANUARY 1993 REVISED AUGUST 2002
D D D D D D D D D
description/ordering information
The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
A1 A2 A3 NC A4 A5 A6
5 6 7 8 9
DIR SAB CLKAB NC VCC CLKBA SBA
4 3 2 1 28 27 26 25 24 23 22 21 20 10 19 11 12 13 14 15 16 17 18
Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.4 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54LVC646A . . . JT OR W PACKAGE SN74LVC646A . . . DB, DW, NS, OR PW PACKAGE (TOP VIEW)
CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8
SN54LVC646A . . . FK PACKAGE (TOP VIEW)
OE B1 B2 NC B3 B4 B5
NC No internal connection
ORDERING INFORMATION
TA PACKAGE SOIC DW DW 40°C to 85°C SOP NS SSOP DB TSSOP PW CDIP JT 55°C to 125°C CFP W LCCC FK Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74LVC646ADW SN74LVC646ADWR SN74LVC646ANSR SN74LVC646ADBR SN74LVC646APWR SNJ54LVC646AJT SNJ54LVC646AW SNJ54LVC646AFK TOP-SIDE MARKING LVC646A LVC646A LC646A LC646A SNJ54LVC646AJT SNJ54LVC646AW
SNJ54LVC646AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A7 A8 GND NC B8 B7 B6
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SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS302I JANUARY 1993 REVISED AUGUST 2002
description/ordering information (continued)
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that are performed with the 'LVC646A devices. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE INPUTS OE X X H H L L L DIR X X X X L L H CLKAB X H or L X X X CLKBA X H or L X H or L X SAB X X X X X X L SBA X X X X L H X A1A8 Input Unspecified Input Input disabled Output Output Input DATA I/O B1B8 Unspecified Input Input Input disabled Input Input Output OPERATION OR FUNCTION OR FUNCTION Store A, B unspecified Store B, A unspecified Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS302I JANUARY 1993 REVISED AUGUST 2002
BUS B
21 OE L
3 DIR L
1 23 CLKAB CLKBA X X
2 SAB X
22 SBA L
21 OE L
3 DIR H
1 CLKAB X
23 CLKBA X
2 SAB L
BUS B 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H BUS B 22 SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
21 OE X X H
3 DIR X X X
1 23 CLKAB CLKBA X X STORAGE FROM A, B, OR A AND B
2 SAB X X X
22 SBA X X X
21 OE L L
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
BUS A 3 DIR L H
BUS A
3
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