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Details, datasheet, quote on part number:SN54LVC74A
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| Part: | SN54LVC74A |
| Category: | Logic => Flip-Flops => CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage |
| Description: | Dual Positive-edge-triggered D-type Flip-flop With Clear And Preset |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN54LVC74A datasheet File size : 318 kB |
| Request For quote: | Find where to buy SN54LVC74A
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Datasheet text preview:
SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SCAS287P JANUARY 1993 REVISED SEPTEMBER 2002
D D D D D
Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C
D D
Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
1C LR
1C LR NC VCC
1CLR 1D 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 2CLR 2D 2CLK 2PRE 2Q 2Q
1
14 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q
1D 1CLK 1PRE 1Q 1Q
2 3 4 5 6 7 8
1CLK NC 1PRE NC 1Q
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2C LR 2D NC 2CLK NC 2PRE
SN54LVC74A . . . J OR W PACKAGE SN74LVC74A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW)
SN74LVC74A . . . RGY PACKAGE (TOP VIEW)
SN54LVC74A . . . FK PACKAGE (TOP VIEW)
VCC
GND
2Q
1Q GND NC
TOP-SIDE MARKING LC74A LVC74A LCV74A LC74A LC74A SNJ54LVC74AJ SNJ54LVC74AW
1D
NC No internal connection
description/ordering information
The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. ORDERING INFORMATION
TA PACKAGE QFN RGY SOIC D 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW CDIP J 55°C to 125°C CFP W Tape and reel Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube ORDERABLE PART NUMBER SN74LVC74ARGYR SN74LVC74AD SN74LVC74ADR SN74LVC74ANSR SN74LVC74ADBR SN74LVC74APWR SNJ54LVC74AJ SNJ54LVC74AW
LCCC FK Tube SNJ54LVC74AFK SNJ54LVC74AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
2Q 2Q
1
SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SCAS287P JANUARY 1993 REVISED SEPTEMBER 2002
description/ordering information (continued)
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
FUNCTION TABLE INPUTS PRE L H L H H CLR H L L H H CLK X X X D X X X H L OUTPUTS Q H L H H L Q L H H L H
H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE CLK C C Q TG C C C D TG TG TG C C
Q C CLR C C
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SCAS287P JANUARY 1993 REVISED SEPTEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply-voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Input-voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Output-voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LVC74A MIN VCC Supply voltage voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 12 24 10 12 24 2 1.5 MAX 3.6 SN74LVC74A MIN 1.65 1.5 0.65×VCC 1.7 2 2 0.35×VCC 0.7 0.8 5.5 VCC 0 0 0.8 5.5 VCC 4 8 12 24 4 8 12 24 10 ns/V mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
VIL VI VO
Low-level input voltage Input voltage Output voltage
IOH
High-level output current output current
mA
IOL
Low-level output current output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature 55 125 40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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