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Details, datasheet, quote on part number:SN54LVC86AFK
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Datasheet text preview:
SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I JANUARY 1993 REVISED OCTOBER 1998
D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Package, Ceramic Chip Carriers (FK), and DIPs (J)
SN54LVC86A . . . J OR W PACKAGE SN74LVC86A . . . D, DB, DGV, OR PW PACKAGE (TOP VIEW)
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3B 3A 3Y
SN54LVC86A . . . FK PACKAGE (TOP VIEW)
1B 1A NC VCC 4B 1Y NC 2A NC 2B
3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description
The SN54LVC86A quadruple 2-input exclusive - OR gate is designed for 2.7-V to 3.6-V VCC operation and the SN74LVC86A quadruple 2-input exclusive - OR gate is designed for 1.65-V to 3.6-V VCC operation. The 'LVC86A devices perform the Boolean function Y = A B or Y = AB + AB in positive logic.
4A NC 4Y NC 3B
NC No internal connection
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN54LVC86A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LVC86A is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each gate) INPUTS A L L H H B L H L H OUTPUT Y L H H L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
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SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I JANUARY 1993 REVISED OCTOBER 1998
logic symbol
1A 1B 2A 2B 3A 3B 4A 4B 1 2 4 5 9 10 12 13 11 4Y 8 3Y 6 =1 3 1Y
2Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, PW, and W packages.
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
EXCLUSIVE OR =1
These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT = EVEN-PARITY ELEMENT 2k ODD-PARITY ELEMENT 2k + 1
The output is active (low) if all inputs stand at the same logic level (i.e., A = B).
The output is active (low) if an even number of inputs (i.e., 0 or 2) are active.
The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I JANUARY 1993 REVISED OCTOBER 1998
recommended operating conditions (see Note 4)
SN54LVC86A MIN VCC Supply voltage voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 12 24 9 0 12 24 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 2 2 1.5 MAX 3.6 SN74LVC86A MIN 1.65 1.5 0.65 × VCC 1.7 2 0.35 × VCC 0.7 0.8 5.5 VCC 0 0 0.8 5.5 VCC 4 8 12 24 4 8 12 24 9 ns/V mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
IOH
High-level output current output current
mA
IOL
Low-level output current output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature 55 125 40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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