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Part: SN54LVTH543JT
Category: Interface and Interconnect -> Transceivers
Description: 3.3-v Abt Octal Registered Transceivers With 3-state Outputs
Company: Texas Instruments, Inc.
Datasheet: Download SN54LVTH543JT datasheet File size : 214 kB
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Datasheet text preview:
SN54LVTH543, SN74LVTH543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS704D AUGUST 1997 REVISED APRIL 1999
D D D D D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (JT) DIPs
SN54LVTH543 . . . JT OR W PACKAGE SN74LVTH543 . . . DB, DGV, DW, OR PW PACKAGE (TOP VIEW)
LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB
SN54LVTH543 . . . FK PACKAGE (TOP VIEW)
A1 OEBA LEBA NC VCC
4 3
description
These octal transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
A2 A3 A4 NC A5 A6 A7
5 6 7 8 9 10
2 1 28 27 26 25 24 23 22 21 20
CEBA B1 B2 B3 B4 NC B5 B6 B7
19 11 12 13 14 15 16 17 18
NC No internal connection
The 'LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A8 CEAB GND NC OEAB LEAB B8
Copyright © 1999, Texas Instruments Incorporated
1
SN54LVTH543, SN74LVTH543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS704D AUGUST 1997 REVISED APRIL 1999
description (continued)
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH543 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LVTH543 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS CEAB H X L L L LEAB X X H L L OEAB X H L L L A X X X L H OUTPUT B Z Z B0 L
H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established
logic symbol§
OEBA CEBA LEBA OEAB CEAB 14 LEAB A1 3 3 4 5 6 7 8 9 10 6D 2 23 1 13 11 1EN3 G1 1C5 2EN4 G2 2C6 1 1 5D 4 22 B1
A2 A3 A4 A5 A6 A7 A8
21 20 19 18 17 16 15
B2 B3 B4 B5 B6 B7 B8
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVTH543, SN74LVTH543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS704D AUGUST 1997 REVISED APRIL 1999
logic diagram (positive logic)
OEBA CEBA LEBA OEAB CEAB LEAB 2 23 1 13 11 14 C1 1D 22 B1
A1
3
C1 1D
To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH543 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH543 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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