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Details, datasheet, quote on part number:SN54LVTH574
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Datasheet text preview:
SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS688F MAY 1997 REVISED NOVEMBER 2002
D D D D
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion
D D D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
SN54LVTH574 . . . FK PACKAGE (TOP VIEW)
VCC
OE
2D 1D OE VCC
3 4 5 6 7 8
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK
1
20 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q
8 9 10 11
description/ordering information
These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. ORDERING INFORMATION
TA PACKAGE QFN RGY SOIC DW DW 40°C to 85°C SOP NS SSOP DB TSSOP PW VFBGA GQN CDIP J 55°C to 125°C CFP W LCCC FK Tape and reel Tube Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74LVTH574RGYR SN74LVTH574DW SN74LVTH574DWR SN74LVTH574NSR SN74LVTH574DBR SN74LVTH574PWR SN74LVTH574GQNR SNJ54LVTH574J SNJ54LVTH574W SNJ54LVTH574FK TOP-SIDE MARKING LXH574 LVTH574 LVTH574 LXH574 LXH574 LXH574 SNJ54LVTH574J SNJ54LVTH574W
SNJ54LVTH574FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
GND
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CLK
8D GND CLK 8Q 7Q
1D 2D 3D 4D 5D 6D 7D 8D
2 3 4 5 6 7
3D 4D 5D 6D 7D
2 1 20 19 18 17 16 15
1Q 2Q 3Q 4Q 5Q 6Q
SN54LVTH574 . . . J OR W PACKAGE SN74LVTH574 . . . DB, DW, NS, OR PW PACKAGE (TOP VIEW)
SN74LVTH574 . . . RGY PACKAGE (TOP VIEW)
14 9 10 11 12 13
1
SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS688F MAY 1997 REVISED NOVEMBER 2002
description/ordering information (continued)
The eight flip-flops of the 'LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
SN74LVTH574 . . . GQN PACKAGE (TOP VIEW) 1 A B C D E 2 3 4 A B C D E
terminal assignments
1 1D 3D 5D 7D GND 2 OE 3Q 4D 7Q 8D 3 VCC 2D 5Q 6D CLK 4 1Q 2Q 4Q 6Q 8Q
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVTH574, SN74LVTH574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS688F MAY 1997 REVISED NOVEMBER 2002
logic diagram (positive logic)
OE CLK 1 11
C1 1D 2 1D
19
1Q
To Seven Other Channels Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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