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Details, datasheet, quote on part number:SN55LBC175J
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Datasheet text preview:
SN55LBC175 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVER
SGLS083A MARCH 1995 REVISED JUNE 2000
D D D D D D D
Meets EIA Standards RS-422-A, RS-423-A, RS-485, and CCITT V.11 Designed to Operate With Pulse Durations as Short as 20 ns Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments Input Sensitivity . . . ± 200 mV Low-Power Consumption . . . 20 mA Max Open-Circuit Fail-Safe Design Common-Mode Input Voltage Range of 7 V to 12 V
J OR W PACKAGE (TOP VIEW)
1B 1A 1Y 1, 2EN 2Y 2A 2B GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4B 4A 4Y 3, 4EN 3Y 3A 3B
description
The SN55LBC175 is a monolithic quadruple differential line receiver with 3-state outputs and is designed to meet the requirements of the EIA Standards RS-422-A, RS-423-A, RS-485, and CCITT V.11. This device is optimized for balanced multipoint bus transmission at data rates up to and exceeding 10 million bits per second. The receivers are enabled in pairs with an active-high enable input. Each differential receiver input features high impedance, hysteresis for increased noise immunity, and sensitivity of ± 200 mV over a common-mode input voltage range of 12 V to 7 V. Fail-safe design ensures that if the inputs are open-circuited, the outputs are always high. This device is designed using the Texas Instruments proprietary LinBiCMOSTM technology allowing low power consumption, high switching speeds, and robustness.
FK PACKAGE (TOP VIEW)
3
2
1
1Y 1, 2EN NC 2Y 2A
VCC 4B
20 19 18 4A 17 4Y 16 NC 15 3, 4EN 14 3Y
4 5 6 7 8 9 10 11 12 13
2B
NC
1A
1B
3B
NC No internal connection
This device offers optimum performance when used with the SN55LBC174 quadruple line driver. The SN55LBC175 is available in the 16-pin CDIP (J) package, a 16-pin CPAK (W) package, or a 20-pin LCCC (FK) package. The SN55LBC175 is characterized over the military temperature range of 55°C to 125°C.
FUNCTION TABLE (each receiver) DIFFERENTIAL INPUTS AB VID 0.2 V 0.2 V < VID < 0.2 V VID 0.2 V X Open circuit ENABLE H H H L H OUTPUT Y H ? L Z H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
GND
NC
3A
1
SN55LBC175 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVER
SGLS083A MARCH 1995 REVISED JUNE 2000
logic symbol
4
logic diagram (positive logic)
4 2 1 6 7
1, 2EN
EN 3
1, 2EN 1A 1B 5 2Y 2A 2B
1A 1B 2A 2B 3, 4EN
2 1 6 7 12
1Y
3
1Y
5
2Y
EN 3, 4EN 11
12 10 9 14 15
3A 3B 4A 4B
10 9 14 15
3Y
3A 3B
11
3Y
13
4Y
4A 4B
13
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the J or W package.
schematics of inputs and outputs
EQUIVALENT OF A AND B INPUTS VCC 100 k A Only Input 18 k 100 k B Only 12 k 1 k Y Output 3 k Input TYPICAL OF ALL OUTPUTS VCC TYPICAL OF EN INPUT VCC
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN55LBC175 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVER
SGLS083A MARCH 1995 REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Input voltage, A or B inputs, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Data and control voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input. DISSIPATION RATING TABLE PACKAGE FK J W TA 25°C POWER RATING 1375 mW 1375 mW 1000 mW DERATING FACTOR ABOVE TA = 25°C 11.0 mW/°C 11.0 mW/°C 8.0 mW/°C TA = 125°C POWER RATING 275 mW 275 mW 200 mW
recommended operating conditions
MIN Supply voltage, VCC Common-mode input voltage, VIC Differential input voltage, VID High-level input voltage, VIH Low-level input voltage, VIL High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA 55 EN inputs inputs 2 0.8 8 16 125 4.75 7 NOM 5 MAX 5.25 12 ±6 UNIT V V V V V mA mA °C
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN55LBC175 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVER
SGLS083A MARCH 1995 REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VIT + VIT Vhys VIK VOH VOL IOZ Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis voltage ( VIT + VIT ) Enable input clamp voltage High-level output voltage Low-level output voltage output voltage High-impedance-state output current II = 18 mA VID = 200 mV, VID = 200 mV, VID = 200 mV, VO = 0 V to VCC VIH = 12 V, VIH = 12 V, VIH = 7 V, VIH = 7 V, VIH = 5 V VIL = 0 V VO = 0 Outputs enabled, Outputs disabled IO = 0, VID = 5 V 80 11 0.9 IOH = 8 mA IOL = 8 mA IOL = 8 mA, TA = 125°C VCC = 5 V, VCC = 0 V, VCC = 5 V, VCC = 0 V, Other inputs at 0 V Other inputs at 0 V Other inputs at 0 V Other inputs at 0 V 0.7 0.8 0.5 0.4 3.5 IO = 8 mA IO = 8 mA TEST CONDITIONS MIN 0.2 45 0.9 4.5 0.3 0.5 0.7 ± 20 1 1 0.8 0.8 ± 20 20 120 20 1.4 µA µA mA mA mA 1.5 TYP MAX 0.2 UNIT V V mV V V V µA
II
Bus input current input current
A or B inputs
IIH IIL IOS ICC
High-level enable input current Low-level enable input current Short-circuit output current Supply current current
All typical values are at VCC = 5 V and TA = 25°C.
switching characteristics, VCC = 5 V, CL = 15 pF
PARAMETER tPHL tPLH tPZH tPZL tPHZ tPLZ tsk(p) tt Propagation delay time high- to low-level output delay time, high to low level output Propagation delay time low- to high-level output delay time, low to high level output Output enable time to high level enable time to high level Output enable time to low level enable time to low level Output disable time from high level disable time from high level Output disable time from low level disable time from low level Pulse skew (|tPHL tPLH|) skew (|t Transition time time TEST CONDITIONS VID = 1.5 V to 1.5 V, , See Figure 1 VID = 1.5 V to 1.5 V, , See Figure 1 See Figure 2 Figure See Figure 3 Figure See Figure 2 Figure See Figure 3 Figure See Figure 1 Figure See Figure 1 Figure TA 25°C 55°C to 125°C 25°C 55°C to 125°C 25°C 55°C to 125°C 25°C 55°C to 125°C 25°C 55°C to 125°C 25°C 55°C to 125°C 25°C 55°C to 125°C 25°C 55°C to 125°C 3 4 23 30 18 17 11 22 MIN 11 TYP 22 MAX 30 35 30 35 40 45 30 35 40 55 30 45 6 7 10 16 UNIT ns ns ns ns ns ns ns ns
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN55LBC175 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVER
SGLS083A MARCH 1995 REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
1.5 V Generator (see Note A) Input 50 Output CL = 15 pF (see Note B) 2V TEST CIRCUIT tPLH 90% Output 10% tt VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. 1.3 V 1.3 V VOL tt 0V 0V 1.5 V tPHL VOH
Figure 1. tPLH and tPHL Test Circuit and Voltage Waveforms
VCC Output 1.5 V CL = 15 pF (see Note B) 5 k Generator (see Note A) 50 See Note C Output S1 Open S1 Input tPZH 1.3 V 1.3 V 0V tPHZ 0.5 V VOH S1 Close 1.4 V 2 k 3V
1.3 V 0V VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. C. All diodes are 1N916 or equivalent.
Figure 2. tPHZ and tPZH Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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