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Details, datasheet, quote on part number:SN55LVDS32J
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Datasheet text preview:
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262H JULY 1997 REVISED MARCH 2000
D D D D D D D D D D
Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard Operates with a Single 3.3-V Supply Designed for Signaling Rate of Up To 400 Mbps Differential Input Thresholds ± 100 mV Max Typical Propagation Delay Time of 2.1 ns Power Dissipation 60 mW Typical per Receiver at 200 MHz Bus-Terminal ESD Protection Exceeds 8 kV Low-Voltage TTL (LVTTL) Logic Output Levels Pin-Compatible with the AM26LS32, MC3486, and µA9637 Open-Circuit Fail Safe
SN55LVDS32 . . . J OR W SN65LVDS32D (Marked as LVDS32 or 65LVDS32) (TOP VIEW)
1B 1A 1Y G 2Y 2A 2B GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4B 4A 4Y G 3Y 3A 3B
SN55LVDS32FK (TOP VIEW)
V CC 3B
16 15 14 13 12 11 10 9 8 7 6 5
NC
1
1A
1B
3
2
20 19 18 4A 17 4Y 16 NC 15 G 14 3Y
description
The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are characterized for operation from 40°C to 85°C. The SN55LVDS32 is characterized for operation from 55°C to 125°C.
1Y G NC 2Y 2A
4 5 6 7 8 9 10 11 12 13
2B
SN65LVDS3486D (Marked as LVDS3486) (TOP VIEW)
GND
NC
1B 1A 1Y 1,2EN 2Y 2A 2B GND
1 2 3 4 5 6 7 8
SN65LVDS9637D (Marked as DK637 or LVDS37) SN65LVDS9637DGN (Marked as L37) (TOP VIEW)
VCC 1Y 2Y GND
1 2 3 4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3A VCC 4B 4A 4Y 3,4EN 3Y 3A 3B 1A 1B 2A 2B
4B
1
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262H JULY 1997 REVISED MARCH 2000
AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) SN65LVDS32D 40°C to 85°C 55°C to 125°C SN65LVDS3486D SN65LVDS9637D -- MSOP (DGN) -- -- SN65LVDS9637DGN -- CHIP CARRIER (FK) -- -- -- SN55LVDS32FK CERAMIC DIP (J) -- -- -- SN55LVDS32J FLAT PACK (W) -- -- -- SN55LVDS32W
'LVDS32 logic diagram (positive logic)
G G 1A 1B 2A 7 2B 3A 3B 4A 4B 10 9 14 15 13 4 12 2 1 6 3 1Y
'LVDS3486D logic diagram (positive logic)
1A 1B 1,2EN 2A 7 2 1 4 3 1Y
'LVDS9637D logic diagram (positive logic)
1A 1B 2A 8 7 6 2 1Y
3 2Y
6 2B
5 2Y
5 2B
5 2Y
3A 11 3Y 3B 3,4EN 4Y 4A 4B
10 9 12 14 15
11
3Y
13
4Y
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262H JULY 1997 REVISED MARCH 2000
Function Tables
SN55LVDS32, SN65LVDS32 DIFFERENTIAL INPUT A, B VID 100 mV 100 mV < VID < 100 mV VID 100 mV X Open ENABLES G H X H X H X L H X G X L X L X L H X L OUTPUT Y H H ? ? L L Z H H SN65LVDS3486 DIFFERENTIAL INPUT A, B VID 100 mV 100 mV < VID < 100 mV VID 100 mV X Open ENABLE EN H X H X H X L H X OUTPUT Y H H ? ? L L Z H H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
logic symbol
G G 4 12
SN55LVDS32, SN65LVDS32 1 EN 1A 1B 1, 2EN 4 2 1 6 7
SN65LVDS3486 EN 3
1Y
1A 1B 2A 2B 3A 3B 4A 4B
2 1 6 7 10 9 14 15
2A 3 1Y 5 2Y 11 2B
5
2Y
3, 4EN 3A
12 10 9 14 15
EN 11
3Y
3B 4A
3Y
13
13
4Y
4B
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Function Table
SN65LVDS9637 DIFFERENTIAL INPUT A, B VID 100 mV 100 mV < VID < 100 mV VID 100 mV Open OUTPUT Y H ? L H 1A 1B 2A 2B
logic symbol
SN65LVDS9637 8 7 6 5 2 1Y
3
2Y
H = high level, L = low level, ? = indeterminate
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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