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Details, datasheet, quote on part number:SN55LVDS32W
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Datasheet text preview:
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262M JULY 1997 REVISED OCTOBER 2002
D D D D D D D D D D
Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard Operate With a Single 3.3-V Supply Designed for Signaling Rate of up to 400 Mbps Differential Input Thresholds ± 100 mV Max Typical Propagation Delay Time of 2.1 ns Power Dissipation 60 mW Typical Per Receiver at 200 MHz Bus-Terminal ESD Protection Exceeds 8 kV Low-Voltage TTL (LVTTL) Logic Output Levels Pin Compatible With AM26LS32, MC3486, and µA9637 Open-Circuit Fail Safe
SN55LVDS32 . . . J OR W SN65LVDS32 . . . D OR PW (Marked as LVDS32 or 65LVDS32) (TOP VIEW)
1B 1A 1Y G 2Y 2A 2B GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4B 4A 4Y G 3Y 3A 3B
SN55LVDS32FK (TOP VIEW)
V CC 3B
16 15 14 13 12 11 10 9 8 7 6 5
NC
1
1A
1B
description
The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are characterized for operation from 40°C to 85°C. The SN55LVDS32 is characterized for operation from 55°C to 125°C.
3
2
20 19 18 4A 17 4Y 16 NC 15 G 14 3Y
1Y G NC 2Y 2A
4 5 6 7 8 9 10 11 12 13
2B
SN65LVDS3486D (Marked as LVDS3486) (TOP VIEW)
GND
NC
1B 1A 1Y 1,2EN 2Y 2A 2B GND
1 2 3 4 5 6 7 8
SN65LVDS9637D (Marked as DK637 or LVDS37) SN65LVDS9637DGN (Marked as L37) SN65LVDS9637DGK (Marked as AXF) (TOP VIEW)
VCC 1Y 2Y GND
1 2 3 4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3A VCC 4B 4A 4Y 3,4EN 3Y 3A 3B 1A 1B 2A 2B
4B
1
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262M JULY 1997 REVISED OCTOBER 2002
AVAILABLE OPTIONS PACKAGE TA (D) SN65LVDS32D 40°C to 85°C 55°C to 125°C SN65LVDS3486D SN65LVDS9637D -- -- -- SMALL OUTLINE (PW) SN65LVDS32PW MSOP -- -- SN65LVDS9637DGN SN65LVDS9637DGK -- CHIP CARRIER (FK) -- -- -- -- SNJ55LVDS32FK CERAMIC DIP (J) -- -- -- -- SNJ55LVDS32J FLAT PACK (W) -- -- -- -- SNJ55LVDS32W SN55LVDS32W
'LVDS32 logic diagram (positive logic)
G G 1A 1B 2A 7 2B 3A 3B 4A 4B 10 9 14 15 13 4 12 2 1 6 3 1Y
SN65LVDS3486D logic diagram (positive logic)
1A 1B 1,2EN 2A 7 2 1 4 3 1Y
SN65LVDS9637D logic diagram (positive logic)
1A 1B 2A 8 7 6 2 1Y
3 2Y
6 2B
5 2Y
5 2B
5 2Y
3A 11 3Y 3B 3,4EN 4Y 4A 4B
10 9 12 14 15
11
3Y
13
4Y
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262M JULY 1997 REVISED OCTOBER 2002
FUNCTION TABLE SN55LVDS32, SN65LVDS32 DIFFERENTIAL INPUT A, B VID 100 mV 100 mV < VID < 100 mV VID 100 mV X Open ENABLES G H X H X H X L H X G X L X L X L H X L OUTPUT Y H H ? ? L L Z H H
FUNCTION TABLE SN65LVDS3486 DIFFERENTIAL INPUT A, B VID 100 mV 100 mV < VID < 100 mV VID 100 mV X Open ENABLE EN H H H L H OUTPUT Y H ? L Z H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
logic symbols
SN55LVDS32, SN65LVDS32 G G 4 12 1 EN 1A 1B 1A 1B 2A 2B 3A 3B 4A 4B 2 1 6 7 10 9 14 15 13 4Y 11 5 2Y 2A 3 1Y 2B 1, 2EN 4 2 1 6 7 SN65LVDS3486 EN 3
1Y
5
2Y
3, 4EN 3A
12 10 9 14 15
EN 11
3Y
3B 4A 4B
3Y
13
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. FUNCTION TABLE SN65LVDS9637 DIFFERENTIAL INPUT A, B VID 100 mV 100 mV < VID < 100 mV VID 100 mV Open OUTPUT Y H ? L H
logic symbol
SN65LVDS9637 1A 1B 2A 2B 8 7 6 5 2 1Y
3
2Y
H = high level, L = low level, ? = indeterminate
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262M JULY 1997 REVISED OCTOBER 2002
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A OR B INPUT VCC EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS VCC TYPICAL OF ALL OUTPUTS VCC
300 k
300 k 50 Input 5 Y Output
A Input 7V
B Input 7V
7V
7V
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V Input voltage range, VI (enables and output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input voltage range, VI (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65_C to 150_C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal. DISSIPATION RATING TABLE PACKAGE D (8) D (16) DGK DGN FK J PW (16) W TA 25°C POWER RATING 725 mW 950 mW 425 mW 2.14 W 1375 mW 1375 mW 774 mW 1000 mW DERATING FACTOR ABOVE TA = 25°C 5.8 mW/°C 7.6 mW/°C 3.4 mW/°C 17.1 mW/°C 11.0 mW/°C 11.0 mW/°C 6.2 mW/°C 8.0 mW/°C TA = 70°C POWER RATING 464 mW 608 mW 272 mW 1.37 W 880 mW 880 mW 496 mW 640 mW TA = 85°C POWER RATING 377 mW 494 mW 221 mW 1.11 W 715 mW 715 mW 402 mW 520 mW TA = 125°C POWER RATING -- -- -- -- 275 mW 275 mW -- 200 mW
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS262M JULY 1997 REVISED OCTOBER 2002
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Magnitude of differential input voltage, |VID| |V Common-mode input voltage, VIC (see Figure 1) SN65 prefix SN55 prefix G, G, 1,2EN, or 3,4EN G, G, 1,2EN, or 3,4EN 0.1 ID 2 | 2.4 3 2 0.8 0.6 NOM 3.3 MAX 3.6 UNIT V V V V
*
|V
ID 2
| V
Operating free-air temperature, TA free air temperature
40 55
VCC 0.8 85 125
°C
COMMON-MODE INPUT VOLTAGE RANGE vs DIFFERENTIAL INPUT VOLTAGE
2.5 VIC Common-Mode Input Voltage Range V
2
Max at VCC > 3.15 V Max at VCC = 3 V
1.5
1
0.5 Min 0 0 0.4 0.5 0.1 0.2 0.3 VID Differential Input Voltage V 0.6
ÁÁ ÁÁ ÁÁ
Figure 1. VIC Versus VID and VCC
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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