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Details, datasheet, quote on part number:SN65LV1212
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Datasheet text preview:
SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F FEBRUARY 2002 REVISED NOVEMBER 2002
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100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212 Chipset (Serializer/Deserializer) Power Consumption <350 mW (Typ) at 40 MHz Synchronization Mode for Faster Lock
SN65LV1021 Serializer
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Lock Indicator No External Components Required for PLL Low-Cost 28-Pin SSOP Package Industrial Temperature Qualified, TA = 40°C to 85°C Programmable Edge Trigger on Clock (Rising or Falling Edge) Flow-Through Pinout for Easy PCB Layout
SN65LV1212 Deserializer
SYNC1 SYNC2 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 TCLK_R/F TCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DVCC DVCC AVCC AGND PWRDN AGND D O+ D O AGND DEN AGND AVCC DGND DGND
AGND RCLK_R/F REFCLK AVCC RI+ RI PWRDN REN RCLK LOCK AVCC AGND AGND DGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 DVCC DGND DVCC DGND ROUT5 ROUT6 ROUT7 ROUT8 ROUT9
description
The SN65LV1021 serializer and SN65LV1212 deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 40 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 480-Mbps payload-encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1021 and SN65LV1212 are characterized for operation over ambient air temperature of 40°C to 85°C.
ORDERING INFORMATION DEVICE Serializer Deserializer PART NUMBER SN65LV1021DB SN65LV1212DB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F FEBRUARY 2002 REVISED NOVEMBER 2002
block diagrams
SN65LVDS1021 SN65LVDS1212
LVDS Parallel-to-Serial Serial-to-Parallel 10 Input Latch DIN A+ A Y+ Y 10 Output Latch DO U T
TCLK_R/F
TCLK (10 MHz to 40 MHz)
PLL
Timing / Control
DEN
PLL
Timing / Control
REFCLK REN LOCK RCLK_R/F RCLK (10 MHz to 40 MHz)
SYNC1 SYNC2
Clock Recovery
functional description
The SN65LV1021 and SN65LV1212 are a 10-bit serializer/deserializer chipset designed to transmit data over differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 40 MHz. The chipset has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down mode, and high-impedance mode. The following sections describe each state of operation. initialization mode Initialization of both devices must occur before data transmission can commence. Initialization refers to synchronization of the serializer and deserializer PLLs to local clocks. When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state, while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs remain in the high-impedance state, while the PLL locks to the TCLK.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F FEBRUARY 2002 REVISED NOVEMBER 2002
functional description (continued)
synchronization mode The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be accomplished in one of two ways:
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Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid a SYNC1 or SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.
When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the deserializer LOCK output directly to SYNC1 or SYNC2.
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Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the serializer to send special SYNC patterns. This allows the SN65LV1212 to operate in open-loop applications. Equally important is the deserializer's ability to support hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK when the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer could enter false lock--falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive multitransition (RMT); see Figure 1 for RMT examples. RMT occurs when more than one low-high transition takes place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the data pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists. Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock pattern changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle. The deserializer does not go into lock unitil it finds a unique four consecutive cycles of data boundary (stop/start bits) at the same position. The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a high-impedance state. The user's system should monitor the LOCK pin in order to detect a loss of synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as previously noted.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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