|
Details, datasheet, quote on part number:SN65LVDS2DBV
| |
Datasheet text preview:
SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
D Meets or Exceeds ANSI TIA/EIA-644
Standard
D Designed for Signaling Rates up to D D D D D D D D
400 Mbps Operates From a 2.4-V to 3.6-V Supply Available in the SOT-23 Package Differential Input Voltage Threshold Less Than 100 mV Propagation Delay Times, 2.5 ns Typical Power Dissipation at 200 MHz Is Typically 60 mW Bus-Pin ESD Protection Exceeds 15 kV Open-Circuit Fail Safe Output is High Impedance With VCC < 1.5 V
VCC GND A
SN65LVDS2 DBV PACKAGE (TOP VIEW) 1 2 3 4 B 5 R
logic diagram
A 3 5 B 4 R
description
The SN65LVDS2 is a single low-voltage differential line receiver in a small-outline transistor package. The inputs comply with the TIA/EIA-644 standard and provide a maximum differential input threshold of 100 mV over an input common-mode voltage range of 0 V to 2.4 V.
Function Table
INPUTS VID = VA VB VID 100 mV 100 mV < VID < 100 mV VID 100 mV OUTPUT R H ? L
Open H When used with a low-voltage differential signaling (LVDS) driver (such as the SN65LVDS1) H = high level, L = low level , ? = indeterminate in a point-to-point or multidrop configuration; data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption.
The high-speed switching of LVDS signals requires the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. TI offers you both the SN65LVDS2, which requires this external resistor, or its companion the SN65LVDT2, which eliminates the need by integrating it with the receiver. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make these devices ideal for battery-powered applications. The SN65LVDS2 is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
equivalent input and output schematic diagrams
VCC VCC
300 k
300 k 5
A Input
B Input 7V 7V 7V
R Output
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V Voltage range (A, B, or R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC+ 0.5 V Electrostatic discharge: A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . CLass 3, A:15 kV, B:600 V R (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLass 3, A:7 kV, B:500 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING
DBV 385 mW 3.1 mW/°C 200 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with no air flow.
recommended operating conditions
MIN Supply voltage, VCC Magnitude of differential input voltage, VID Commonmode in ut voltage, VIC (see Figure 6) input Operating freeair temperature, TA 2.4 0.1 0 NOM 3.3 MAX 3.6 0.6 2.4 * UNIT V V
V2D I
V °C
40
VCC0.8 85
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE
3
VIC Common-Mode Input Voltage V
2.5 VCC = 3.6 V 2 VCC = 2.7 V 1.5 VCC = 2.4 V
1
0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 |VID| Differential Input Voltage V
Figure 1. VIC vs VID and VCC
electrical characteristics over recommended operating conditions, VCC = 2.4 to 3 V (unless otherwise noted)
PARAMETER VITH+ VITH VOH VOL ICC II IID Positive-going differential input voltage threshold Negative-going differential input voltage threshold High-level output voltage Low-level output voltage Supply current Input current (A or B inputs) current (A or inputs) Differential input current (IIA IIB) See Figure 2 and Table 1 Figure and Table IOH = 8 mA IOL = 8 mA No load, Steady state VI = 0 V VI = 2.4 V or VCC 0.8 VIA = 0 V, VIB = 0.1 V VIA = 2.4 V VIB = 2.3 V, VCC = 0 V, VI = 2.4 V 100 1.9 2.4 0.25 4 0.4 7 ±20 1.2 ±2 ±20 TEST CONDITIONS MIN TYP MAX 100 mV V V mA µA µA µA UNIT
II(OFF) Power-off input current (A or B inputs) All typical values are at 25°C and with a 2.7-V supply.
receiver switching characteristics over recommended operating conditions, VCC = 2.4 to 2.7 V (unless otherwise noted)
PARAMETER tPLH tPHL tsk(p) tr Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Pulse skew (|tpHL tpLH|) Output signal rise time CL = 10 pF, 10 F See Figure 3 Figure TEST CONDITIONS MIN 1.4 1.4 TYP 2.6 2.5 0.1 0.8 MAX 3.6 3.6 0.6 1.4 1.4 UNIT ns ns ns ns ns
tf Output signal fall time 0.8 All typical values are at 25°C and with a 2.7-V. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
|
|
