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Details, datasheet, quote on part number:SN65LVDT33D
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| Part: | SN65LVDT33D |
| Category: | Interface and Interconnect => LVDS (Low Voltage Differential Signaling) |
| Description: | ti SN65LVDT33, Quad LVDS Receiver With -4 to 5V Common-mode Range |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN65LVDT33D datasheet File size : 278 kB |
| Request For quote: | Find where to buy SN65LVDT33D
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Datasheet text preview:
SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS490A MARCH 2001 REVISED MAY 2001
D D D D D D D D D D D D
400-Mbps Signaling Rate1 and 200-Mxfr/s Data Transfer Rate Operates With a Single 3.3-V Supply 4-V to 5-V Common-Mode Input Voltage Range Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range Integrated 110- Line Termination Resistors On LVDT Products TSSOP Packaging (33 Only) Complies With TIA/EIA-644 (LVDS) Active Failsafe Assures a High-Level Output With No Input Bus-Pin ESD Protection Exceeds 15 kV HBM Input Remains High-Impedance on Power Down TTL Inputs Are 5-V Tolerant Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B
SN65LVDS33D SN65LVDT33D SN65LVDS33PW SN65LVDT33PW
D OR PW PACKAGE (TOP VIEW)
logic diagram (positive logic)
G G
SN65LVDT33 ONLY
1B 1A 1Y G 2Y 2A 2B GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4B 4A 4Y G 3Y 3A 3B
1A 1Y 1B 2A 2B 3A 3B 4A 4B 4Y 3Y
2Y
SN65LVDS34D SN65LVDT34D
D PACKAGE (TOP VIEW)
description
This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option. Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.
VCC 1Y 2Y GND
logic diagram (positive logic) 1A 1B 2A 2B
1A 1Y 1B
SN65LVDT34 ONLY
1 2 3 4
8 7 6 5
2A 2B
2Y
AVAILABLE OPTIONS
PART NUMBER NUMBER TERMINATION OF RESISTOR RECEIVERS 4 4 4 4 2 2 No No Yes Yes No Yes SYMBOLIZATION
SN65LVDS33D SN65LVDS33PW SN65LVDT33D SN65LVDT33PW SN65LVDS34D SN65LVDT34D
LVDS33 LVDS33 LVDT33 LVDT33 LVDS34 LVDT34
Add the suffix R for taped and reeled carrier.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS490A MARCH 2001 REVISED MAY 2001
description (continued)
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note. The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from 40°C to 85°C. Function Tables
SN65LVDS33 and SN65LVDT33 DIFFERENTIAL INPUT VID = VA VB VID -32 mV 32 mV 100 mV < VID 32 mV mV 32 mV VID 100 mV 100 mV X Open ENABLES G H X H X H X L H X G X L X L X L H X L OUTPUT Y H H ? ? L L Z H H SN65LVDS34 and SN65LVDT34 DIFFERENTIAL INPUT VID = VA VB VID -32 mV 100 mV < VID 32 mV VID -100 mV Open H = high level, L = low level, ? = indeterminate OUTPUT Y H ? L H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS490A MARCH 2001 REVISED MAY 2001
equivalent input and output schematic diagrams
VCC Attenuation Network VCC 1 pF 60 k A Input 200 k 3 pF 250 k 7V 7V 6.5 k Attenuation Network 6.5 k Attenuation Network
B Input 7V 7V
LVDT Only 110 VCC VCC 300 k (G Only) 100
Enable Inputs 7V
37 Y Output 7V 300 k
(G Only)
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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