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Details, datasheet, quote on part number:SN65LVDT348D
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| Part: | SN65LVDT348D |
| Category: | Interface and Interconnect => LVDS (Low Voltage Differential Signaling) |
| Description: | ti SN65LVDT348, Quad LVDS Receiver With -4 to 5V Common-mode Range |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN65LVDT348D datasheet File size : 490 kB |
| Request For quote: | Find where to buy SN65LVDT348D
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Datasheet text preview:
SN65LVDS348, SN65LVDT348 SN65LVDS352, SN65LVDT352
SLLS523D - FEBRUARY 2002 - REVISED FEBRUATY 2003
QUAD HIGH SPEED DIFFERENTIAL RECEIVERS
FEATURES D Meets or Exceeds the Requirements of ANSI D D D D D
TIA/EIA-644A Standard Single-Channel Signaling Rates1 up to 560 Mbps -4 V to 5 V Common-Mode Input Voltage Range Flow-Through Architecture Active Failsafe Assures a High-level Output When an Input Signal Is not Present SN65LVDS348 Provides a Wide Common-Mode Range Replacement for the SN65LVDS048A or the DS90LV048A
APPLICATIONS D Logic Level Translator D Point-to-Point Baseband Data Transmission D D D
Over 100- Media ECL/PECL-to-LVTTL Conversion Wireless Base Stations Central Office or PABX Switches
DESCRIPTION
The SN65LVDS348, SN65LVDT348, SN65LVDS352, and SN65LVDT352 are high-speed, quadruple differential receivers with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The `348 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The `352 adds two additional VCC and GND pins in a 24-pin package to provide higher data transfer rates with multiple receivers in operation. All offer a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110- line termination resistor.
DATA TRANSFER RATE vs FREE-AIR TEMPERATURE
550 SN65LVDS352PW 500 Data Transfer Rate - Mxfr/s
450 400 SN65LVDS348PW 350 300 250 200 -60 215 -1 prbs NRZ, VID = 0.4 V VIC = 1.2 V, CL = 5.5 pF, 40% Open Eye 4 Receivers Switching, Input Jitter < 45 ps -40 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 100
Timer LVDT Device Only
(One of Four Shown) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002 - 2003 Texas Instruments Incorporated
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SLLS523D - FEBRUARY 2002 - REVISED FEBRUATY 2003
SN65LVDS348, SN65LVDT348 SN65LVDS352, SN65LVDT352
description (continued)
These receivers also provide 3x the standard's minimum common-mode noise voltage tolerance. The -4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface. Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent-pending) failsafe circuit that provides a high-level output approximately 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space requirements and parts count by eliminating the need for a separate termination resistor. This can also improve signal integrity at the receiver by reducing the stub length from the line termination to the receiver. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from -40°C to 85°C.
SN65LVDS348, SN65LVDT348 D or PW PACKAGE (TOP VIEW) SN65LVDS352, SN65LVDT352 PW PACKAGE (TOP VIEW)
RIN1- RIN1+ RIN2+ RIN2- RIN3- RIN3+ RIN4+ RIN4-
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
EN ROUT1 ROUT2 VCC GND ROUT3 ROUT4 EN
1A 1B 2A 2B EN 1,2 VCCA AGND EN 3,4 3A 3B 4A 4B
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
NC 1Y DGND1 VCCD1 2Y NC NC 3Y VCCD2 DGND2 4Y NC
NC - No internal connection
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SLLS523D - FEBRUARY 2002 - REVISED FEBRUATY 2003
SN65LVDS348, SN65LVDT348 SN65LVDS352, SN65LVDT352
To One Other Receiver
functional block diagrams (one of four receivers shown)
348 Devices EN EN RIN+ ROUT1 RIN- Timer SN65LVDT348 Only SN65LVDT352 Only B Timer EN A Y To Three Other Receivers 352 Devices
Window Comparator AVAILABLE OPTIONS PART NUMBER SN65LVDS348D SN65LVDT348D SN65LVDS348PW SN65LVDT348PW SN65LVDS352PW n n INTEGRATED TERMINATION PACKAGE TYPE SOIC SOIC TSSOP TSSOP TSSOP
Window Comparator
PACKAGE MARKING LVDS348 LVDT348 DL348 DE348 DL352
SN65LVDT352PW n TSSOP DE352 Add the R suffix to the device type (e.g., SN65LVDS348DR) for taped and reeled carrier.
Function Tables
348 DEVICES INPUTS VID = VRIN+ - VRIN- VID -32 mV -100 mV < VID < -32 mV VID -100 mV Open X EN H H H H L or OPEN X 352 DEVICES INPUTS VID = VIA - VIB VID -32 mV -100 mV < VID < -32 mV VID -100 mV X Open EN H H H L or OPEN H OUTPUTS Y H ? L Z H EN L or OPEN L or OPEN L or OPEN L or OPEN X H OUTPUTS RO U T H ? L H Z Z
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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