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Details, datasheet, quote on part number:SN65LVDT388
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Datasheet text preview:
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A SEPTEMBER 2000 REVISED MAY 2001
D D D D D D D D D D D
Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard Integrated 110- Line Termination Resistors on LVDT Products Designed for Signaling Rates Up To 630 Mbps SN65 Version's Bus-Terminal ESD Exceeds 15 kV Operates From a Single 3.3-V Supply Propagation Delay Time of 2.6 ns (Typ) Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns LVTTL Levels Are 5-V Tolerant Open-Circuit Fail Safe Flow-Through Pin Out Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch
NOT RECOMMENDED FOR NEW DESIGNS For Replacement Use 'LVDx388A
'LVDS388, 'LVDT388 DBT PACKAGE (TOP VIEW)
description
The `LVDS388 and `LVDT388 (T designates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight differential receivers will provide a valid logical output state with a +100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT product eliminates this external resistor by integrating it with the receiver.
A1A A1B A2A A2B NC B1A B1B B2A B2B NC C1A C1B C2A C2B NC D1A D1B D2A D2B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
GND VCC ENA A1Y A2Y ENB B1Y B2Y GND VCC GND C1Y C2Y ENC D1Y D2Y END VCC GND
logic diagram (positive logic)
'LVDx388
'LVDT388 ONLY
1A 1Y 1B EN 2A 2B (1/4 of 'LVDx388 shown)
2Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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· DALLAS, TEXAS 75265
1
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A SEPTEMBER 2000 REVISED MAY 2001
description (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over 150 million data transfers per second in single-edge clocked systems are possible with very little power. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics. The SN65LVDS388 and SN65LVDT388 is characterized for operation from 40°C to 85°C. The SN75LVDS388 and SN75LVDT388 is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS PART NUMBER SN65LVDS388DBT SN65LVDT388DBT SN75LVDS388DBT SN75LVDT388DBT TEMPERATURE RANGE 40°C to 85°C 40°C to 85°C 0°C to 70°C 0°C to 70°C NUMBER OF RECEIVERS 8 8 8 8 BUS-PIN ESD 15 kV 15 kV 4 kV 4 kV
Function Table
SNx5LVD388 and SNx5LVDT388 DIFFERENTIAL INPUT A-B VID 100 mV -100 mV < VID 100 mV VID -100 mV X Open ENABLES EN H H H L H OUTPUT Y H ? L Z H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
VCC VCC VCC
300 k
300 k 400 EN Y Output 5
A Input 7V 7V
B Input
7V 300 k
7V
110 'LVDT Devices Only
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A SEPTEMBER 2000 REVISED MAY 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V Electrostatic discharge: (see Note 2) SN65' (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:15 kV, B: 700 V SN75' (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2, A:4 kV, B: 400 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 25°C
PACKAGE
TA 25°C
TA = 70°C POWER RATING
TA = 85°C POWER RATING 556 mW
DBT 1071 mW 8.5 mW/°C 688 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Magnitude of differential input voltage, VID |V Common-mode input voltage, VIC (see Figure 4) SN75' Operating free-air temperature, TA free-air tem SN65' Enables Enables 0.1 ID 2 | 2.4 3 2 0.8 0.6 I * |V2D| NOM 3.3 MAX 3.6 UNIT V V V V
V °C °C
0 40
VCC 0.8 70 85
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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