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Details, datasheet, quote on part number:SN65LVDT388ADBT
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Datasheet text preview:
SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394E SEPTEMBER 1999 REVISED SEPTEMBER 2002
D D D D D D D D D D D
Four ('390), Eight (`388A), or Sixteen (`386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard Integrated 110- Line Termination Resistors on LVDT Products Designed for Signaling Rates Up To 630 Mbps SN65 Version's Bus-Terminal ESD Exceeds 15 kV Operates From a Single 3.3-V Supply Typical Propagation Delay Time of 2.6 ns Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns LVTTL Levels Are 5-V Tolerant Open-Circuit Fail Safe Flow-Through Pin Out Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch
'LVDS388A, 'LVDT388A DBT PACKAGE (TOP VIEW)
'LVDS386, 'LVDT386 DGG PACKAGE (TOP VIEW)
description
This family of four, eight, or sixteen differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight or sixteen differential receivers will provide a valid logical output state with a ±100 mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.
A1A A1B A2A A2B AGND B1A B1B B2A B2B AGND C1A C1B C2A C2B AGND D1A D1B D2A D2B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
GND VCC ENA A1Y A2Y ENB B1Y B2Y DGND DVCC DGND C1Y C2Y ENC D1Y D2Y END VCC GND
See application section for VCC and GND description. 'LVDS390, 'LVDT390 D OR PW PACKAGE (TOP VIEW)
1A 1B 2A 2B 3A 3B 4A 4B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
EN1,2 1Y 2Y VCC GND 3Y 4Y EN3,4
A1A A1B A2A A2B A3A A3B A4A A4B B1A B1B B2A B2B B3A B3B B4A B4B C1A C1B C2A C2B C3A C3B C4A C4B D1A D1B D2A D2B D3A D3B D4A D4B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND VCC VCC GND ENA A1Y A2Y A3Y A4Y ENB B1Y B2Y B3Y B4Y GND VCC VCC GND C1Y C2Y C3Y C4Y ENC D1Y D2Y D3Y D4Y END GND VCC VCC GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394E SEPTEMBER 1999 REVISED SEPTEMBER 2002
description (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8- or 16-channel driver, the SN65LVDS389 or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
AVAILABLE OPTIONS PART NUMBER SN65LVDS386DGG SN65LVDT386DGG SN75LVDS386DGG SN75LVDT386DGG SN65LVDS388ADBT SN65LVDT388ADBT SN75LVDS388ADBT SN75LVDT388ADBT SN65LVDS390D SN65LVDS390PW SN65LVDT390D SN65LVDT390PW SN75LVDS390D SN75LVDS390PW SN75LVDT390D SN75LVDT390PW TEMPERATURE RANGE 40_C to 85_C 40_C to 85_C 0_C to 70_C 0_C to 70_C 40_C to 85_C 40_C to 85_C 0_C to 70_C 0_C to 70_C 40_C to 85_C 40_C to 85_C 40_C to 85_C 40_C to 85_C 0_C to 70_C 0_C to 70_C 0_C to 70_C 0_C to 70_C NUMBER OF RECEIVERS 16 16 16 16 8 8 8 8 4 4 4 4 4 4 4 4 BUS-PIN ESD 15 kV 15 kV 4 kV 4 kV 15 kV 15 kV 4 kV 4 kV 15 kV 15 kV 15 kV 15 kV 4 kV 4 kV 4 kV 4 kV SYMBOLIZATION LVDS386 LVDT386 75LVDS386 75LVDT386 LVDS388A LVDT388A 75LVDS388A 75LVDT388A LVDS390 LVDS390 LVDT390 LVDT390 75LVDS390 DS390 75LVDT390 DG390
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS394E SEPTEMBER 1999 REVISED SEPTEMBER 2002
logic diagram (positive logic)
'LVDx386
'LVDT386 ONLY
'LVDx388A
'LVDT388A ONLY
'LVDx390
'LVDT390 ONLY
1A 1Y 1B 2A 2B EN 3A 3B 4A 4B (1/4 of 'LVDx386 shown) 4Y
1A 1Y 1Y 1B EN 2A 2B 3A 3B EN 4A 4B ('LVDx390 shown) 3Y
1A 1B EN 2A 2B
2Y
2Y
2Y
3Y
(1/4 of 'LVDx388A shown)
4Y
Function Table
SNx5LVD386/388A/390 and SNx5LVDT386/388A/390 DIFFERENTIAL INPUT A-B VID 100 mV -100 mV < VID 100 mV VID -100 mV X Open ENABLES EN H H H L H OUTPUT Y H ? L Z H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
VCC VCC VCC
300 k
300 k 400 EN Y Output 5
A Input 7V 7V
B Input
7V 300 k
7V
110 'LVDT Devices Only
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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