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Details, datasheet, quote on part number:SN74221
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| Part: | SN74221 |
| Category: | Logic => Multivibrators/Oscillators => Low Voltage CMOS/BiCMOS->LVC/ALVC/VCX Family |
| Description: | Dual Monostable Multivibrator With With Schmitt-trigger Inputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74221 datasheet File size : 213 kB |
| Request For quote: | Find where to buy SN74221
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Datasheet text preview:
SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
SDLS213A DECEMBER 1983 REVISED FEBRUARY 1998
D D D D D
Dual Versions of Highly Stable SN54121 and SN74121 One Shots SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots Pinout Is Identical to the SN54123, SN74123, SN54LS123, and SN74LS123 Overriding Clear Terminates Output Pulse Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flat Packs (W), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
MAXIMUM OUTPUT PULSE LENGTH(S) 21 28 49 70
SN54221, SN54LS221 . . . J OR W PACKAGE SN74221 . . . N PACKAGE SN74LS221 . . . D, DB, OR N PACKAGE (TOP VIEW)
1A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A
SN54LS221 . . . FK PACKAGE (TOP VIEW)
TYPE SN54221 SN74221 SN54LS221 SN74LS221
description
The '221 and 'LS221 devices are monolithic dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transitiontriggered input and a positive-transition-triggered input, either of which can be used as an inhibit input.
1CLR 1Q NC 2Q 2Cext
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1B 1A NC VCC 1R ext /Cext 1Cext 1Q NC 2Q 2CLR
NC No internal connection
Copyright © 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, is also provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from 35 ns to the maximums shown in the above table by choosing appropriate timing components. With Rext = 2 k and Cext = 0, an output pulse typically of 30 ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics waveforms. Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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· DALLAS, TEXAS 75265
2R ext/Cext
GND NC 2A 2B
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SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
SDLS213A DECEMBER 1983 REVISED FEBRUARY 1998
description (continued)
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 k to 30 k for the SN54221, 2 k to 40 k for the SN74221, 2 k to 70 k for the SN54LS221, and 2 k to 100 k for the SN74LS221). Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 0.7 CextRext. In circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 k can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed. The variance in output pulse width from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the '221 is shown in Figure 3. Variations in output pulse width versus supply voltage and temperature for the '221 are shown in Figures 4 and 5, respectively. Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the '221 or 'LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed. The SN54221 and SN54LS221 are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74221 and SN74LS221 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE (each monostable multivibrator) INPUTS CLR L X X H H A X H X L L B X X L H H OUTPUTS Q L L L Q H H H
Pulsed-output patterns are tested during AC switching at 25°C with Rext = 2 k, and Cext = 80 pF. This condition is true only if the output of the latch formed by the two NAND gates has been conditioned to the logic 1 state prior to CLR going high. This latch is conditioned by taking either A high or B low while CLR is inactive (high).
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
SDLS213A DECEMBER 1983 REVISED FEBRUARY 1998
logic symbol
1A 1B 1 2 & 1 13 1Q
1CLR 1Cext
3 14 15
R CX RX/CX & 1
4
1Q
1Rext/Cext 2A 2B
9 10
5 11
2Q
2CLR 6 2Cext 2Rext/Cext 7
R CX RX/CX
12
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, and W packages.
timing component connections
VCC Rext
To Cext Terminal
To Rext/Cext Terminal
NOTE: Due to the internal circuit, the Rext/Cext terminal is never more positive than the Cext terminal.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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