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Details, datasheet, quote on part number:SN74ABT126DR
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| Part: | SN74ABT126DR |
| Category: | Logic => Buffers/Drivers => Non-Inverting Buffers and Drivers |
| Description: | ti SN74ABT126, Quadruple Bus Buffer Gates With 3-State Outputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74ABT126DR datasheet File size : 303 kB |
| Request For quote: | Find where to buy SN74ABT126DR
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Datasheet text preview:
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183H FEBRUARY 1991 REVISED MAY 2003
D D D
Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down High-Drive Outputs (32-mA IOH, 64-mA IOL)
D D D
Ioff and Power-Up 3-State Support Hot Insertion Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
SN54ABT126 . . . FK PACKAGE (TOP VIEW)
1OE
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4OE 4A 4Y 3OE 3A 3Y
1
14 13 4OE 12 4A 11 4Y 10 3OE 9 3A
VCC
1A 1Y 2OE 2A 2Y
2 3 4 5 6 7 8
1Y NC 2OE NC 2A
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1A 1OE NC VCC 4OE 4A NC 4Y NC 3OE
NC No internal connection ORDERABLE PART NUMBER SN74ABT126RGYR SN74ABT126N SN74ABT126D SN74ABT126DR SN74ABT126NSR SN74ABT126DBR SN74ABT126PW SN74ABT126PWR SNJ54ABT126J TOP-SIDE MARKING AB126 SN74ABT126N ABT126 ABT126 AB126 AB126 SNJ54ABT126J
Copyright 2003, Texas Instruments Incorporated
SN54ABT126 . . . J PACKAGE SN74ABT126 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
SN74ABT126 . . . RGY PACKAGE (TOP VIEW)
description/ordering information
The 'ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION
TA PACKAGE QFN RGY PDIP N SOIC D 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW PW 55°C to 125°C to 125°C CDIP J Tape and reel Tube Tube Tape and reel Tape and reel Tape and reel Tube Tape and reel Tube
LCCC FK Tube SNJ54ABT126FK SNJ54ABT126FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
GND
· DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
3Y
1
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183H FEBRUARY 1991 REVISED MAY 2003
FUNCTION TABLE (each buffer) INPUTS OE H H L A H L X OUTPUT Y H L Z
logic diagram (positive logic)
1OE 1A 1 2 3 3OE 1Y 3A 10 9 8
3Y
2OE 2A
4 5 6
4OE 2Y 4A
13 12 11
4Y
Pin numbers shown are for the D, DB, J, N, NS, PW, and RGY packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183H FEBRUARY 1991 REVISED MAY 2003
recommended operating conditions (see Note 4)
SN54ABT126 MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate 200 0 4.5 2 0.8 VCC 24 48 10 200 0 MAX 5.5 SN74ABT126 MIN 4.5 2 0.8 VCC 32 64 10 MAX 5.5 UNIT V V V V mA mA ns/V µs/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL Vhys II IOZPU IOZPD IOZH IOZL Ioff ICEX IO§ ICC VCC = 4 5 V 4.5 TEST CONDITIONS CONDITIONS II = 18 mA IOH = 3 mA IOH = 3 mA IOH = 24 mA IOH = 32 mA IOL = 48 mA IOL = 64 mA 100 VCC = 0 to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE 0.8 V VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE 0.8 V VCC = 0, VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0 55V 0, VI = VCC or GND or GND VCC = 5.5 V, One input at 3.4 V, input at 3 4 V Other inputs at VCC or GND VI = 2.5 V or 0.5 V VI or VO 4.5 V Outputs high VO = 2.5 V Outputs high Outputs low Outputs disabled Outputs enabled Outputs disabled 3 50 100 1 24 0.5 ±1 ±50 ±50 10 10 ±100 50 200 250 30 250 1.5 50 50 50 200 250 30 250 1.5 50 50 ±1 ±50 ±50 10 10 ±1 ±50 ±50 10 10 ±100 50 200 250 30 250 1.5 50 MIN 2.5 3 2 2* 0.55 0.55* 0.55 0.55 TA = 25°C TYP MAX 1.2 2.5 3 2 2 V mV µA µA µA µA µA µA µA mA µA mA µA mA µA pF pF SN54ABT126 MIN MAX 1.2 2.5 3 V SN74ABT126 MIN MAX 1.2 UNIT V
VOH
ICC¶ Ci
Co VO = 2.5 V or 0.5 V 7 * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. For VCC between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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